We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67150

2016.1 - Simulation Libraries - Compiling Simulation Libraries also includes IP


I have noticed that when I run Vivado in Tcl mode and run compile_simlib, IP are also compiled in Vivado 2016.1. 

I do not see this behavior in the GUI when I run compile_simlib. 

Is this expected behavior? How do I use these libraries in simulation?

If I do not want to compile these IP libraries, how do I disable them in Tcl mode?


Starting in Vivado 2016.1 compile_simlib (in Tcl mode) will compile the static simulation files for IPs by default.

In the Vivado IDE this option is disabled by default.

If you do not wish to compile IP simulation libraries you can use the -no_ip_compile switch with compile_simlib while in Tcl mode or just compile within the GUI.

IP simulation libraries are not currently used in Vivado 2016.1. It is an Early Access feature that can be enabled by request.

For more information on how to enable pre-compiled IP simulation libraries during simulation please refer to (Xilinx Answer 66928).

AR# 67150
Date 05/09/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.1
Page Bookmarked