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AR# 67164

UltraScale+ Memory IP - timing failures occur due to high congestion levels


Version Found: v2.0

Version Resolved: See (Xilinx Answer 58435)

UltraScale+ DDR4, DDR3, and RLDRAM3 IP interfaces that are placed in HD banks adjacent to HP I/Os can fail timing due to a high congestion level which impacts routability. 

A high congestion level is 5 or greater and Vivado will generate the following INFO message:

INFO: [Route 35-448] Estimated routing congestion is level 6 (64x64). Congestion levels of 5 and greater can reduce routability and impact timing closure.

These timing failures have a higher probability to occur under the following conditions:

  • Targeting Kintex+ devices - xcku9p-ffve900, xcku13p-ffve900
  • Targeting Zynq+ device - xczu9eg-ffvb1156
  • DDR4, DDR3, and RLDRAM3 IP (QDRII+ and QDRIV IP are not impacted)
  • Placed in HD banks adjacent to HP I/Os
  • 64-bit and 72-bit wide interfaces



The following are suggestions we recommend to bypass the timing failures:

  1. If possible, move the interface I/O to different banks that do not share a clock region adjacent to HP I/Os.
  2. Manually create and set a user PBLOCK constraint for the Memory IP that spans across two horizontal clock regions.

Revision History:

05/05/2016 - Initial Release

Linked Answer Records

Master Answer Records

AR# 67164
Date 05/09/2016
Status Active
Type Known Issues
  • Kintex UltraScale+
  • Zynq UltraScale+ MPSoC
  • MIG UltraScale