Version Found: DDR4 v2.0, DDR3 v1.2, RLDRAM3 v1.2
Version Resolved: See (Xilinx Answer 58435)
UltraScale+ DDR4, DDR3, and RLDRAM3 IP interfaces that are placed in HD banks adjacent to HP I/Os can fail timing due to a high congestion level which impacts routability.
A high congestion level is 5 or greater and Vivado will generate the following INFO message:
These timing failures have a higher probability to occur under the following conditions:
The following are suggestions we recommend to bypass the timing failures:
05/05/2016 - Initial Release