We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67179

MIG 7 Series - Memory clock period range is updated in Vivado 2016.2 and may cause errors during IP upgrade


If you are upgrading a MIG IP generated using older Vivado versions (any version prior to 2016.2) and its maximum frequency is updated in Vivado 2016.2, errors similar to the following might be seen in the console:

[xilinx.com:ip:mig_7series:4.0-0] mig_7series_0: - Memory Time Period (1875 PS) (533.333 MHz) is not supported for MIG. There has been a change in the allowed frequency ranges as described in Answer Record 67179. Instantiate and customize a new instance of MIG for your design

This is due to the updates made to MIG v4.0.


Updates have been made to the frequency ranges for some configurations in the MIG IP in the 2016.2 release.

These were done to fully align with the datasheet and device supported speeds. We recommend following these guidelines for all new designs going forward.

If the above error occurs, create a new MIG IP from scratch in Vivado 2016.2, customize it as per your earlier IP settings and choose a new clock period within the allowed clock period range.

Designs requiring earlier clock periods should contact Xilinx Technical Support.

Revision History:


AR# 67179
Date 06/08/2016
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • Artix-7
  • MIG 7 Series