AR# 67225

UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IP

Description

Version Found: DDR4 v2.0 (Rev. 1). DDR3 v1.2 (Rev. 1), RLDRAM3 v1.2 (Rev. 1), QDRII+ v1.2 (Rev. 1), QDRIV v1.1 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

(PG150) states that the Memory IP will automatically generated the CLOCK_DEDICATED_ROUTE BACKBONE constraint if the "No Buffer" option is not used. Why do I not see the constraint added?

Solution

This is a known issue that can be resolved by manually adding the CLOCK_DEDICATED_ROUTE BACKBONE constraint using the following syntax:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

Note: When using the "No Buffer" option the CLOCK_DEDICATED_ROUTE BACKBONE constraint must always be applied manually. Refer to (PG150) for more details.

https://www.xilinx.com/cgi-bin/docs/ipdoc?c=mig;v=latest;d=pg150-ultrascale-memory-ip.pdf

Revision History:

05/13/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 67225
Date 12/20/2017
Status Active
Type Known Issues
Devices More Less
Tools
IP