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AR# 67255

UltraScale/UltraScale+ DDR4 - [Place 30-487] error may occur for some configurations


Version Found: DDR4 v2.0

Version Resolved: See (Xilinx Answer 69035)

UltraScale and UltraScale+ DDR4 SDRAM IP interfaces might fail with the following error if not enough resources are available to fit inside the existing Pblock:

ERROR: [Place 30-487] The packing of instances into a set of CLBs defined by an internal area constraint could not be obeyed. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.


If the above error message is seen, one of the following methods can be used to bypass the error:

  • Manually create and set a user PBLOCK constraint for the Memory IP that spans across two horizontal clock regions.
  • Use the command "set_param place.generateMIGPblock false" in the Tcl console

Revision History:

05/20/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67255
Date 01/02/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • MIG UltraScale
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