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AR# 67320

Kintex/Virtex/Zynq UltraScale+ MPSoC: Incorrect GTH/GTY CPLL Frequency

Description

The Kintex/Virtex/Zynq UltraScale+ MPSoC GTH/GTY transceiver CPLL might not be able to lock reliably after configuration or removing/re-applying the reference clock or asserting/de-assserting CPLLPD.

In the failure state, the CPLL might be stuck at an invalid output frequency and the CPLLLOCK signal might incorrectly be high.

Solution

 

For the UltraScale+ GTH/GTY CPLL to lock reliably, the CPLL calibration block should be used to ensure that the CPLL locks reliably and acquires the correct frequency.

 

The GT Wizard can generate this block automatically but this is not currently included by default and none of the GT Wizard based Parent IPs that use CPLL have this turned on in Vivado 2016.2 or Vivado 2016.3.

To turn on the CPLL calibration block in the Wizard, the work-around below should be followed.

This is enabled/turned on automatically by the Wizard in Vivado 2017.2 and this CPLL information will also be added to the UltraScale Architecture GTH/GTY Transceivers user guides (UG576 and UG578) in a future revision.

It is enabled/turned automatically by the PCIe IP beginning in Vivado 2017.1.

 

Work-around:

 

Vivado version
GT Wizard version
Notes regarding CPLL calibration module from GT Wizard
2016.3/2016.4
v1.6
Not enabled by default.
Must use Tcl command to enable.

CPLL calibration module has a bug where if  the user issues a subsequent CPLLRESET in the middle of the CPLL calibration operation, the original user TX_PROGDIV_CFG value is lost.
This will cause issues if TXPROGDIV path is used by user afterwards.
2017.1
v1.6
Not enabled by default.
Must use Tcl command to enable.

Fixed above mentioned reset in the middle of calibration bug.
Delayed powergood work-around for GTY can be enabled via Tcl command.
Delayed powergood not yet available for GTH.
2017.2
v1.7
Enabled by default if CPLL is selected when configuring in GT Wizard.
Delayed powergood work-around is present for both GTH and GTY by default.

CPLL calibration enhanced to account for cases where TX might be using QPLL and RX is using CPLL, and TX cannot be interrupted.
Original code always performed the CPLL calibration using the TX side of the CHANNEL.

 

Tcl command to enable CPLL calibration module in 2016.3/2016.4/2017.1:

set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gtwizard_ultrascale_0]
 

Tcl command to enable GTPOWERGOOD delay for GTY in 2017.1:

 
set_property -dict [list CONFIG.USER_GTPOWERGOOD_DELAY_EN {1} ] [get_ips gtwizard_ultrascale_0]

 

 

If the IP is generated from the Vivado GUI, please follow the steps below.

1) Generate the GT wizard design.

2) Run the following command in the Tcl console:

set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gtwizard_ultrascale_0]

3) Select the GT wizard IP .xci file and reset the output products.

4) Generate the GT wizard design again.

Linked Answer Records

Associated Answer Records

AR# 67320
Date 06/20/2017
Status Active
Type General Article
Devices
  • Kintex UltraScale+
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
IP
  • IO Interfaces
  • UltraScale FPGA Transceiver Wizard