I am doing a VHDL simulation and I am getting a setup violation on CLKA with respect to CLK B, or setup violation on CLKB with respect to CLKA. It does this for every clock edge.
I am using a Virtex Block ram in my design, and I am using the same clock for PORT A and PORT B. I have the Port A and Port B adress' at different locations.
How can I be getting setup violation on the clocks when I am using the same clock for both ports?
Solution
The problem you are experiencing is an error in the VHDL simulation model for the RAMB4. The following is the change that will fix the problem. This fix is implemented in the Xilinx 2.1i release. After making the following changes the library will have to be re-compiled.
In every model for [X_]RAMB4_S*_S* in simprim and unisim libraries in Port B code, the following lines should change:
line 11832(In my copy) in 1.5 was if (VALID_ADDRB AND Tviol_CLKB_CLKA_posedge /= 'X') then DOB_zd := MEM((ADDRESS_B*DIBW + DIBW_1) downto (ADDRESS_B*DIBW)); else DOB_zd := (others => 'X'); end if;
should change to:
if (VALID_ADDRB ) then if ( WEA_ipd = '0' OR Tviol_CLKB_CLKA_posedge /= 'X' OR (HAS_OVERLAP = FALSE)) then DOB_zd := MEM((ADDRESS_B*DIBW + DIBW_1) downto (ADDRESS_B*DIBW)); end if; else DOB_zd := (others => 'X'); end if;
The vhd file will need to be re-compiled for the changes to take effect.
This is fixed in 2.1i
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AR# 6733
Date
09/30/2008
Status
Archive
Type
General Article
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