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AR# 67330

Zynq UltraScale+ MPSoC - PS DDR Pin Swap Guidelines

Description

Which pins can be swapped on a Zynq UltraScale+ PS DRAM interface?

Solution

A byte lane includes any signals associated with the aligned 8-bits of DQ, such as DM, DQS, DQS_N, DBI and DQ signals.

Information on Zynq UltraScale+ PS DDR pin swapping can be found in (UG1075) - Zynq UltraScale+ MPSoC Packaging and Pinouts Product Specification

Note that additional pin swap restrictions are required if using the (infrequently used) Write CRC feature of DDR4. See (Xilinx Answer 68788) for the additional restrictions and how to enable the feature.

AR# 67330
Date 03/03/2017
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
IP
  • Zynq UltraScale+ MPSoC Processing System
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