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AR# 67336

UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) mode

Description

Version Found: v1.2 (Rev. 1)

Version Resolved: See (Xilinx Answer 69038)

When generating the UltraScale QDRII+ IP output products in Out-Of-Context (OOC) mode, the IP should generate a *_ooc.xdc constraints file.

The create_clock constraint for the IP is included in this file. If the *_ooc.xdc constraints file is missing, then the create_clock for the IP does not get included during synthesis and an accurate timing estimate will not be provided.

Solution

The solution is to manually add a create_clock constraint for the input reference clock to the QDRII+ IP into the top-level XDC constraints file.

This issue will be fixed in a future IP release.

Revision History:

06/06/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69038 QDRII+ UltraScale and UltraScale+ IP Release Notes and Known Issues N/A N/A
AR# 67336
Date 12/15/2017
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2016.2
IP
  • QDRII+ SRAM
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