Version Found: v1.2 (Rev. 1)
Version Resolved: See (Xilinx Answer 69038)
When generating the UltraScale QDRII+ IP output products in Out-Of-Context (OOC) mode, the IP should generate a *_ooc.xdc constraints file.
The create_clock constraint for the IP is included in this file. If the *_ooc.xdc constraints file is missing, then the create_clock for the IP does not get included during synthesis and an accurate timing estimate will not be provided.
The solution is to manually add a create_clock constraint for the input reference clock to the QDRII+ IP into the top-level XDC constraints file.
This issue will be fixed in a future IP release.
06/06/2016 - Initial Release