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AR# 67354

JESD204 PHY - CPLLPD is not held high for at least 2us


The UltraScale Transceiver User Guides (UG576) and (UG578) state that CPLLPD (which is used to reset the CPLL) must be held high for at least 2us to ensure that the CPLL is properly reset.

The JESD204 PHY core does not meet this timing requirement when using the external reset pins (tx_sys_reset and rx_sys_reset). This issue only appears in designs that use CPLL.


To ensure that the timing requirement is met on the CPLLPD pin, it is recommended to enable the AXI4-Lite interface on the core and hold register 0x408 high for at least 2us for all UltraScale and UltraScale+ designs using CPLL

If the JESD204 PHY is being used as part of the JESD204 IP (JESD204 has been generated with Shared Logic in the core) it is recommended to generate the JESD204 IP with "Shared Logic in Example Design" and then generate the JESD204 PHY separately and include the AXI4-Lite interface.

This will allow access to register 0x408.

This has been resolved in the 2016.3 release of the JESD204 PHY IP (v3.2).

AR# 67354
Date 11/25/2016
Status Active
Type Known Issues
  • Virtex UltraScale
  • Kintex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • JESD204
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