Version Found: RLDRAM3 v1.2
Version Resolved: See (Xilinx Answer 69037)
The RLDRAM3 IP incorrectly generates 20 address bits for 576Mb x36 parts and 21 address bits for 1.125Gb x36 parts which only requires 19 and 20 address bits respectively.
This causes problems during implementation and I/O Planning because the RLDRAM3 component does not physically have that many address bits.
To work around this issue, please create a Custom Memory Part using the import CSV flow in the IP GUI with the correct number of address bits specified.
Refer to (Xilinx Answer 63462) for more details on creating a Custom Memory Part.
06/13/2016 - Initial Release