Upon assertion of the PROG_B signal, a LOW pulse < 500pS (150nS - 500nS) can be seen on the I2C_SCL pin.
The PROG_B assertion will interrupt the SYSMON I2C port and this can cause clock stretching or data corruption if the I2C Master is an active bus during FPGA device configuration.
Note: This issue has only been seen in UltraScale devices and not on UltraScale+ devices.
If the design has a central reset controller that controls both the I2C Master and the FPGA reset, then the PROG_B assertion can be done prior to releasing the reset of the I2C Master.
In other cases where the I2C master is active continuously, external circuitry must be added to gate the UltraScale I2C_SCL pin.
For instance, most I2C translators have built-in EN circuitry to gate one side of the translator.