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AR# 67392

UltraScale and UltraScale+ Memory IP - pulse width violations can occur

Description

Version Found: v2.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

The UltraScale and UltraScale+ Memory IP incorrectly allows input clock frequencies greater than allowed which can result in pulse width violations when checking timing.

Solution

To prevent pulse width violations, ensure that the input clock frequency selected in the Memory IP GUI is within the supported range as defined in the DC and AC Switching Characteristics Data Sheet (DS923, DS922, DS893, DS892) for the target FPGA device.


DS923 Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
DS922 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
DS893 Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
DS892 Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics


Revision History:

06/15/2016

AR# 67392
Date Created 06/15/2016
Last Updated 06/22/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
IP
  • MIG UltraScale