This answer record contains the Release Notes and Known Issues for the UltraScale+ Integrated 100G Ethernet Subsystem and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.1 and later versions.
UltraScale+ Integrated 100G Ethernet Subsystem Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Core Version||Vivado Tools Version|
|v2.4 (Rev. 2)||2018.1|
|v2.4 (Rev. 1)||2017.4|
|v1.0 (Rev. 1)||2016.2|
The table below provides Answer Records for general guidance when using the LogiCORE UltraScale Interlaken core.
Table 2: General Guidance
|Article Number||Article Title|
|(Xilinx Answer 55248)||Vivado Timing and IP constraints|
|(Xilinx Answer 61626)||How do I speed up simulation?|
|(Xilinx Answer 62457)||How do I generate a license key to activate this core?|
Known and Resolved Issues
The following table provides known issues for the UltraScale Interlaken core, starting with v1.0, initially released in Vivado 2016.1.
Note: The "Version Found" column lists the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 3: IP Known and Resolved Issues
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 70775)||Example design errors out if TX Flow control is enabled, but RX flow control is disabled||v2.4||See Answer Record|
|(Xilinx Answer 67965)||Timing errors seen on some devices when GT RX Buffer bypass is used||v2.0||See Answer Record|
|NA||Updated GT DRP registers for runtime switching between CAUI-4 and CAUI-10||v1.0||v1.1 (REV. 1)|
|6/8/2016||Added GT DRP register update|