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AR# 67422

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2016.2) - Link up failure after multiple resets

Description

Version Found: 4.2 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 57945)

An issue has been identified in the UltraScale FPGA Gen3 Integrated Block for PCI Express core where after multiple resets, the link fails to come up.

The ltssm state constantly toggles between Detect.Quiet and Detect.Active states after the failure occurs.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in the next release of the core. To fix the issue in Vivado 2016.2, please install the patch attached to this Answer Record as described below:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR67422
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3. Run Vivado software tools from the original install location.


METHOD 2:

  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR67422\vivado\
  4. Run Vivado software tools from the original install location.


If the fixes need to be applied manually, the following files in which the changes have been made in the patch, have been attached with this answer record from

  1. The core generated with the patch (Modified_Files_With_Patch_Vivado_2016_2.zip)
  2. The core generated without the patch (Modified_Files_Without_Patch_Vivado_2016_2.zip).

  • pcie3_ultrascale_0_gtwizard_top.v
  • pcie3_ultrascale_0_init_ctrl.v

Please compare the two sets of files and apply the changes in your design accordingly. Also make the following changes in the IP constraint file:

Change from the following:

set_false_path -from [get_pins {gt_top_i/phy_rst_i/idle_reg/C}] -to [get_pins {pcie3_uscale_top_inst/init_ctrl_inst/reg_phy_rdy_reg[0]/D}]

Change to the following:

set_false_path -from [get_pins {gt_top_i/phy_rst_i/idle_reg/C}] -to [get_pins {pcie3_uscale_top_inst/init_ctrl_inst/reg_phy_rdy_reg[*]/PRE}
set_false_path -from [get_pins {gt_top_i/phy_rst_i/idle_reg/C}] -to [get_pins {pcie3_uscale_top_inst/init_ctrl_inst/reg_reset_timer_reg[*]/CLR}]

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

07/19/2016 - Initial release

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57945 UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues N/A N/A
AR# 67422
Date Created 06/21/2016
Last Updated 11/14/2016
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)