Version Found: 4.2 (Rev1)
Version Resolved and other Known Issues: (Xilinx Answer 57945)
An issue has been identified in the UltraScale FPGA Gen3 Integrated Block for PCI Express core where after multiple resets, the link fails to come up.
The ltssm state constantly toggles between Detect.Quiet and Detect.Active states after the failure occurs.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This is a known issue to be fixed in the next release of the core. To fix the issue in Vivado 2016.2, please install the patch attached to this Answer Record as described below:
If the fixes need to be applied manually, the following files in which the changes have been made in the patch, have been attached with this answer record from
Please compare the two sets of files and apply the changes in your design accordingly. Also make the following changes in the IP constraint file:
Change from the following:
Change to the following:
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/19/2016 - Initial release