AR# 6743: VHDL simulation RAM16X1D: Can not perform a write unless all inputs are at a known level
VHDL simulation RAM16X1D: Can not perform a write unless all inputs are at a known level
Keywords: RAM, RAM16X1D, write, vhdl
I can not perform a write operation. I have the write address (A3 to A0) at a known level, have a valid clock, data at a known level, and we is high. The only input that is not at a known level is the (read) dpra pins, which is at an unknown value. It should not matter what the read address is at so how come I can not do a write?
This is a VHDL simulation model problem that is currently being looked into by development.
Currently during simulation if a write operation is to be performed then the user must ensure that all inputs are at a known level.