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AR# 67455

UltraScale DDR3 and DDR4 IP - ECC signals are missing from the User Interface when ECC is enabled without AXI


Version Found: DDR3 and DDR4 IP v2.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

When ECC is enabled for DDR3 and DDR4 IP without AXI the following signals are missing from the User Interface (UI):

  • ecc_err_addr
  • ecc_single
  • ecc_multiple
  • app_wdf_mask

These signals are required for proper error reporting and for DDR4 Partial Write support when using the ECC module.


In order to resolve this issue the attached tactical IP patch should be installed. This patch contains added ports for proper ECC functionality and to support Partial Writes.

To install the patch, extract the contents of "AR67455_Vivado_2016_2_preliminary_rev1.zip" to the 2016.2 install directory (for example, C:\Xilinx\Vivado\2016.2\), then open Vivado 2016.2 and generate or regenerate all of the DDR3 and DDR4 IP.

Note: This tactical patch is only compatible with the Vivado 2016.2 DDR3 and DDR4 v2.0 (Rev. 1) IP.

Revision History:

07/21/2016 - Initial Release

10/07/2016 - Updated to include DDR3


Associated Attachments

Name File Size File Type
AR67455_Vivado_2016_2_preliminary_rev2.zip 3 MB ZIP
AR# 67455
Date 10/13/2016
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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