AR# 67455


UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI


Version Found: DDR4 v2.0 (Rev. 1), DDR3 1.2 (Rev. 1)

Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036)

When ECC is enabled for DDR3 and DDR4 IP without AXI the following signals are missing from the User Interface (UI):

  • ecc_err_addr
  • ecc_single
  • ecc_multiple
  • app_wdf_mask

These signals are required for proper error reporting and for DDR4 Partial Write support when using the ECC module.


In order to resolve this issue the attached tactical IP patch should be installed. 

This patch contains added ports for proper ECC functionality and to support Partial Writes.

To install the patch, extract the contents of "" to the 2016.2 install directory (for example, C:\Xilinx\Vivado\2016.2\), then open Vivado 2016.2 and generate or regenerate all of the DDR3 and DDR4 IP.

Note: This tactical patch is only compatible with the Vivado 2016.2 DDR3 v1.2 (Rev. 1) and DDR4 v2.0 (Rev. 1) IP.

Revision History:

07/21/2016 - Initial Release

10/07/2016 - Updated to include DDR3


Associated Attachments

Name File Size File Type 3 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 67455
Date 01/02/2018
Status Active
Type Known Issues
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