In Zynq UltraScale+ MPSoC devices, when R5 is the boot master, FSBL boots from R5 and loads a user application to start from the A53 master. However, A53 fails to Boot.
How can I resolve this?
Technically A53 Application code can be compiled from any starting address including 0x0, which is a DDR location from A53's point of view.
As per MPSoC architecture, R5 sees address location 0x00 as a TCM load address, instead of as a DDR location.
As a result it tries to load the A53 user application ELF into TCM instead of DDR and hands off to the A53.
A53 fails to boot because the image is never loaded into the DDR.
Change the Linker script of the A53 user application manually and set the application start address to 0x100000 (i.e. 1MB).
This address is visible to R5 and A53 as a DDR location.
This will resolve the 0x00 address view issue with R5, and A53 booting goes ahead as normal.