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AR# 67544

DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.


Version Found: Initial DDR4/DDR3 UltraScale IP Release

Version Resolved: See (Xilinx Answer 58435)

An issue with the DDR4/DDR3 user interface has been identified where the data presented is from a future read from the same address. When this occurs, a data error would be triggered. After the data error, app_rdy might get stuck low and the read buffer stay full forever.

This issue can occur with any type of DDR4/3 traffic pattern although it is extremely rare for this lock condition to occur. The issue has been seen in both hardware and simulation. The error is not seen when using the Strict Ordering mode of the controller.

Including the attached patch is recommended.


Issue Details:

The User Interface sends the same read data buffer address (dBufAdr) a second time to the memory controller before the memory controller has finished writing back the first read data into the read buffer. This causes the unrecoverable lock condition.

If the stuck behavior occurs, it would look similar to the following example:


Attached to this answer record are patches for Vivado 2016.1 and 2016.2 to resolve this issue as well as instructions on patch installation. 

If a patch for a previous version is required, please open a Service Request.


Associated Attachments

AR# 67544
Date 08/26/2016
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale+
  • MIG UltraScale
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