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AR# 67599

2016.2 Vivado - ERROR: [Place 30-876] Port 'clk' is assigned to PACKAGE_PIN 'G14' which can only be used as the N side of a differential clock input.


I am seeing the following error during place_design:

ERROR: [Place 30-876] Port 'clk'  is assigned to PACKAGE_PIN 'G14'  which can only be used as the N side of a differential clock input. 
Please use the following constraint(s) to pass this DRC check:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {clk_IBUF_inst/O}]
Resolution: Please use the xdc constraints above.
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

How do I resolve this error?


This error occurs when a clock port is assigned to the N side of clock capable pins. Only the P side has the dedicating routing connection needed for optimal routing and so non-differential clocks should be assigned to P side locations for optimal routing. 

To override this type of error, and accept the non-optimal use of the N side of clock capable pins, you can use one of the following methods:

1) Add CLOCK_DEDICATED_ROUTE constraints to the XDC file as stated in the error message. For example:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {clk_IBUF_inst/O}]

2) Set CLOCK_BUFFER_TYPE constraints in the RTL code to prevent the synthesis tool from inserting a BUFG. For example:

(* clock_buffer_type="none" *) input clk;
AR# 67599
Date 08/16/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1