UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67671

GMII to RGMII - CRITICAL WARNING: [Constraints 18-853] create_generated_clock: master clock not found.

Description

When a GMII to RGMII core is used in a block design, the following constraint fails to process during synthesis:

create_generated_clock -add -name rgmii_tx_clk -divide_by 1 -source [get_pins -of [get_cells -hier -filter{name =~ *rgmii_txc_out}] -filter {name =~ *CLK}] -master_clock [get_clocks gmii_clk_125m*] [get_ports rgmii_txc]

Vivado issues the following critical warning.

CRITICAL WARNING: [Constraints 18-853] create_generated_clock: master clock not found.[project_1/project_1.srcs/sources_1/bd/tcd_ps_bd/ip/tcd_ps_bd_gmii_to_rgmii_0_0/synth/tcd_ps_bd_gmii_to_rgmii_0_0_clocks.xdc:27]

Solution

This critical warning is resolved when the constraint is updated as follows:

create_generated_clock -add -name rgmii_tx_clk -divide_by 1 -source [get_pins -of [get_cells -hier -filter {name =~ *rgmii_txc_out}] -filter {name =~ *CLK}] -master_clock [get_clocks -of [get_ports gmii_clk_125m*]] [get_ports rgmii_txc]

 

 

 

 

The issue is seen when an IP configured in Shared Logic and an IP configured in Example design are connected with each other.

 

 

Revision History:

 

8/5/2016 - Initial Release

AR# 67671
Date Created 08/04/2016
Last Updated 08/19/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.2
IP
  • GMII to RGMII