AR# 67674

Description

This article describes how to analyze and debug UltraScale/UltraScale+ issues involving clock partitioning errors.

Solution

With global clock networks that can be segmented in UltraScale/UltraScale+ architectures, designs can see contention for clocking resources when a large number of global clocks are needed for a particular clock region. 

There are several types of clock partitioning errors, and it is usually helpful to view the resolution suggestion at the end of each individual error.

Messaging - Below are examples of partitioning error messages.

ERROR: [Place 30-835] Clock partitioning failed to resolve contention in clock region X0Y4. Only a maximum of 24 global clock nets can use resources in a clock region, however, there are 27 clocks in this region as listed below.
These clock nets either have user-constrained loads or have IO loads placed by the tool. If the clock sources/loads have constraints, please ensure they are placed close to each other to avoid using routing resources in other regions.
List of nets sourced in this region along with their unmovable loads (first 10 loads):

Delay matching for global Clocks:

ERROR: [Place 30-894] Cannot match clock delays for global clock nets 'net1' and 'net2'. Placer is trying to match clock delays for these clocks for best timing, but this operation failed due to usage of these tracks by other clock nets.
Try reducing the amount of clock resources in your design, by either combining some clock nets or by changing the placement of clock primitives to reduce the distance between the source and loads of each clock net involved in clock region <clock_region_value> and areas with high clock routing utilization.

Analysis - Analyzing the report_clock_utilization output is a good place to start. 

While the "Place 30-835" error will give you a list of clocks in the problem clock region, other errors do not. 

With place_design errors, the I/O and clock placement information is erased after the failure. 

Therefore, using the place_ports command is recommended to analyze the clock utilization.

The place_ports command will keep the I/O and clock placement progress, even after a failure. This allows for further debug of an issue. Below is an example of the command:

report_clock_utilization -file clk_util.rpt

The clk_util.rpt will give you information on the resources currently used.

• Global Clock Summary - This shows areas of high global clock utilization. The bolded clock regions would be possible areas of contention. A list of each clock per clock region is also provided.

• Routing Resource Utilization - A breakdown of utilization for horizontal and vertical distribution and routing tracks is given in this section.

All Modules - Total Usage Sums of Static and RP modules

Suggestions - Both example messages are an indication of global clock resource contention.  

1. Reduce the number of clocks or clocking resources in the design.
• Remove MMCM feedback paths if unnecessary.
• Use the shared resource option when generating multiple IPs with global clocking structures.
• Combine identical clocks.
2. Make sure to use CLOCK_REGION constraints to constrain global buffers instead of LOC constraints. LOC constraints add limitations to placement by fixing routing tracks, but the CLOCK_REGION constraint does not.
3. View the clock utilization report and floorplan. "report_clock_utilization -file clk_util.rpt"
4. Limit resources used by low fanout clocks. If a low fanout clock is using a large number of clock regions, this can be limited in a few ways.
• Using a pblock on the clock loads will contain the global clock resources used.
• CLOCK_LOW_FANOUT constraint. Applied to the output of a global clock buffer, the CLOCK_LOW_FANOUT constraint will limit the clock loads to a single clock region.
5. Limit global clocks that traverse large distances. Global clocks that traverse long distances will use global clock routing resources, and will limit resources for other clocks. The same methods that can be applied to low fanout clocks can also be applied here.
6. If successfully routed versions of the same design are available as a comparison, visually inspect the global clocks using the Vivado Find functionality.
   Opening the Device Window with the Routing Resources enabled and selecting a clock will show what clock regions are used. An example image of this is shown below.
• Specifically, look to see if low fanout clocks (Flat Pin Column) pass through too many clock regions. These can be contained with the above suggestions.

To understand details of the clock utilization report, refer to the "Report Clock Utilization" section in (UG906) Vivado Design Suite User Guide: Design Analysis and Closure Techniques

(UG949) Ultrafast Design Methodology Guide has a detailed section on "Clocking Guidelines" 

For more details on UltraScale clocking architecture refer to (UG572)