AR# 67675

40G/50G Ethernet Subsystem - How can I speed up simulation?


The example design simulation can take several hours to complete.

Is there a way to speed up the simulation?


Simulations involving the complex transceiver models can take long periods of time to complete.

If your simulation involves the 40G/50G Ethernet Sub-System operating in a loopback scenario, an additional method to improve simulation time is to reduce the PCS lane Alignment Marker (AM) spacing in order to speed up the time the IP will take to achieve PCS Lane lock.

In 2016.3 and later versions of the core, the simulation can be sped up by setting 'define SIM_SPEED_UP:


Use the vlogan option +define+SIM_SPEED_UP


Use the vlog option +define+SIM_SPEED_UP


Use the ncvlog option +define+SIM_SPEED_UP

Vivado Simulator:

Use the xvlog option -d SIM_SPEED_UP

In earlier versions of the core, this can be achieved by changing CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default of 16'h3FFF to 16'h03FF.


  1. Altering the value of CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default value of 0x3FFF will violate the IEEE 802.3 specification.
  2. Decreasing the AM spacing will result in less than 40G/50G bandwidth being available on the link. If using a PCS only core, this can result in TX buffer overflow for larger frames.
  3. This change can be made only in simulation. For a design to work in hardware, the default value of 0x3FFF must be used.
  4. Full rate simulation without the SIM_SPEED_UP option should still be run.
AR# 67675
Date 04/18/2017
Status Active
Type General Article