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AR# 67684

UltraScale/UltraScale+ Memory IP - moving IP that uses custom memory parts (CSV) might cause problems


Version Found: DDR4 v2.0 (Rev. 1), DDR3 v1.2 (Rev. 1), RLDRAM3 v1.2 (Rev. 1), QDRII+ v1.2 (Rev. 1), QDRIV v1.1 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

When moving an existing Memory IP that uses a custom memory part (CSV file), the following errors message might be seen:

[Common 17-55] 'set_property' expects at least one object. ["/ddr4/ddr4_0_example.srcs/constrs_1/imports/par/example_design.xdc":78]
[Mig 66-99] Memory Core Error - [u_ddr4_0] Port(s) c0_ddr4_bg[0],c0_ddr4_bg[1] is/are not placed. Assign all ports to valid sites.
[Synth 8-524] part-select [151:144] out of range of prefix 'mcal_ADR' ["/ddr4/ddr4_0_example.srcs/sources_1/ip/ddr4_0/ip_0/rtl/map/ddr4_0_phy_ddrMapDDR4.vh":254]
[Synth 8-2715] syntax error near , ["/ddr4/ddr4_0_example.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0_ddr4.sv":184]


These problems can occur when the memory IP is moved into a new Vivado Project or Managed IP project, and the CSV file cannot be found. 

This results in corrupted output products being generated.

Currently, the only work-around is to generate a new Memory IP from scratch using the same custom memory part (CSV) and options. 

This issue will be fixed in a future release of Vivado.

Revision History:

08/08/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 67684
Date 01/02/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite - 2016.2
  • MIG UltraScale
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