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AR# 67714

v7ht.tcl silently fails to place and route GTZ-related logic


When using the IP Catalog to generate GTZ transceivers, an encrypted Tcl script named v7ht.tcl is required to Place and Route the beachfront logic that is connected to the GTZ.

The script must run in order for timing to be guaranteed on the interface. Because the script is encrypted and produces no output in a log file, when it fails to run, it is a silent failure that the user cannot detect it without knowing what the script is supposed to do.

Old versions of the GTZ IP cannot be opened as synthesized checkpoints in the 2016.x releases because the logic funneling will automatically remove the LUT1s that are required for the script to execute. 

The IP needs to be modified and regenerated with DONT_TOUCH attributes in place to prevent logic funneling that occurs during Synthesis and linking.


The script requires hand-instantiated non-inverting LUT1s to be included in the beachfront IP in order to create directed route constraints through the LUTs to the Flip-Flops that are placed in the same slice.

The root cause of the problem is that logic-funneling occurs where the non-inverting LUT1s are automatically dissolved. When that happens, there is no way for the script to complete.

The solution to the problem is to use DONT_TOUCH attributes on the LUT1 wires in Verilog as shown in the attached RTL. The GT Wizard IP needs to be resynthesized with the DONT_TOUCH attributes in place in order for the script to run.

There are several ways to verify that the script did run. One of the operations is to PROHIBIT certain BELs in the die. Looking for the presence of the highlighted red PROHIBIT sites in the optimized checkpoint is one way to see if the script ran.

Another Tcl-based approach is to run the attached v7ht_verify.tcl script which will ensure that there are at least 100 fixed cells with the string gtz in them, 100 prohibited bels and 100 fixed routes. The verify script gives a good indication that the v7ht.tcl script ran as expected.


Associated Attachments

AR# 67714
Date 08/31/2016
Status Active
Type General Article
  • Virtex-7 HT
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • 7 Series FPGAs Transceivers Wizard
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