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AR# 67719

UltraScale GTH/GTY Transceiver Startup Current


This answer record covers startup current that can occur under some specific conditions in the UltraScale GTH/GTY transceivers.

This information will be added to the UltraScale Architecture GTH and GTY Transceivers User Guides, (UG576) and (UG578).


The process of initializing and activating the circuits in the transceivers begins at the end portion of FPGA configuration.

During this time, the circuits in the transceiver are powered up and the configuration settings from the bit file are applied to the transceiver. 

Control of the transceiver ports from the FPGA logic is also activated. All of these actions occur over a period of time that begins with the last few FPGA programming clocks and finishes when the FPGA fabric is fully activated.

The process of configuring the FPGA is explained in detail in the UltraScale Architecture Configuration User Guide, (UG570).

For the UltraScale GTH/GTY transceiver (not UltraScale+ GTH/GTY) under certain conditions there can be significant current loading on the power supplies MGTAVCC, MGTAVTT and MGTVCCAUX in the period of time just prior to the end of configuration when the DONE pin signal is asserted.

The occurrence of these current spikes depends on the timing of the programming clock and the FPGA programming bus width. Given the FPGA programming bus width, if the time to execute the number of configuration clock cycles in Table 1 is greater than 64 us, significant current loading spikes can occur in the time period just prior to the assertion of the DONE pin signal.

After the assertion of DONE, the power consumption of the transceiver will be in compliance with the power consumption reported by XPE and by Report Power in Vivado.

Table 1: Number of programming clock cycles before end of configuration

FPGA Configuration Bus WidthConfiguration Clock Cycles

The FPGA programming clock is not required to be symmetrically periodic. So, the 64 us criteria is dependent on the time required to execute the number of clock cycles even if they have a large variation in period.

If the time to execute the number of clock cycles in Table 1 is greater than 64 us, the startup timing of the transceiver can be adjusted by modifying the POR_RAMP_TIME which is the lower 4 bits of the POR_CFG attribute. 

Table 2 below gives the approximate delay for each setting of the POR_RAMP_TIME. Increasing the POR_RAMP_TIME will increase the time allowed to execute the number for clock cycles in Table 1. 

The POR_CFG is an attribute of the GTHE3_COMMON/GTYE3_COMMON primitive. Therefore, to adjust the POR_RAMP_TIME, the GTH3_COMMON/GTYE3_COMMON primitive must be instantiated in the design.

Table 2: POR_RAMP_TIME settings and associated POR delay

POR_RAMP_TIME SettingPOR Delay (us)

Note 1: Default setting for POR_RAMP_TIME in the POR_CFG attribute.

How to modify the attribute:

The attribute POR_CFG can be modified either in the RTL source code or in Vivado after implementation using Tcl commands.

To modify the RTL, locate the file generated by the transceiver wizard, [Component Name]_gt[h or y]3_common_wrapper.v and locate the attribute GT[H or Y]E_COMMON_POR_CFG.

Then modify the 4 least significant bits to set the POR Delay as shown in Table 2.

For example:

In the file [Component Name]_gth3_common_wrapper.v, change the attribute GTHE3_COMMON_POR_CFG. 

In the file, find the attribute which will appear as follows:

.GTHE3_COMMON_POR_CFG (16'b0000000000000100),

The lower 4 bits are modified to change the POR_RAMP_TIME. 

For example, to change the POR_RAMP_TIME to a value of 0x7, the changed parameter in the file would be:

.GTHE3_COMMON_POR_CFG (16'b0000000000000111),

To change the POR_CFG attribute after implementation and prior to bitstream generation, use the following Tcl command:

set_property POR_CFG 16'h0007 [get_cells Path_to_primitive.GTHE3_COMMON_PRIM_INST]
AR# 67719
Date 11/03/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
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