Using the available pin swapping feature from Vivado in an UltraScale Design results in some nets being partially routed.
In some cases, the GUI will show zero under the "Failed Routes" column from the Design Runs tab.
However, opening the Implemented design and running the report_route_status command will show the conflicts.
How can I work around this?
This issue can be caused by a portion of a synthesized design having placement information (XDEF) for GT elements.
The GTs are contained within a DCP which is added to the full project. In the full project, I/O port constraints conflict with the original GT constraints. The problem is that both the old and new GT (CHANNEL) locations are kept, which causes the routing to fail.
There are a number of options for working around this issue when using Vivado 2016.2:
For example, the package pin constraints for a REFCLK will either be MGTREFCLK0P or MGTREFCLK1P. If the package pin with the '1' distinction is used, then this must connect to the IBUFDS1_GTE3, and GTREFCLK1 pin of the GTHE3_CHANNEL primitive.
Using the MGTREFCLK0P and GTREFCLK1 pin would require pin swapping.
Also, if the GTHE3_CHANNEL is placed in a different clock region from the I/O package pins, then the appropriate GTNORTHREFCLKx pin should be used. (UG576) will have more information on the expected connectivity.
Below is an image of a path that would not need the pin swapping involving the MGTREFCLK0_* package_pin, IBUFDS0_GTE3 buffer, and the GTREFCLK0 GTHE3_CHANNEL pin.
In this case, The GTHE3_CHANNEL is placed in the same clock region as the I/O package pins.