Using the available pin swapping feature from Vivado in an UltraScale Design results in some nets being partially routed.
In some cases, The GUI will show zero under the "Failed Routes" column from the Design Runs tab. However, opening the Implemented design and running the report_route_status command will show the conflicts.
How can I work around this?
This issue is currently scheduled to be fixed in the 2016.3 version of Vivado which is due in October.
To work around the issue, it is necessary to adjust the logical design so that the pin swapping feature is not needed. This means aligning the logical design in accordance with the dedicated paths from a GTREFCLK input, through an IBUFDS_GTE3, to the correct REFCLK pin.
The work-around would normally involve one of two options:
For example, the package pin constraints for a REFCLK will either be MGTREFCLK0P or MGTREFCLK1P. If the package pin with the '1' distinction is used, then this must connect to the IBUFDS1_GTE3, and GTREFCLK1 pin of the GTHE3_CHANNEL primitive. Using the MGTREFCLK0P and GTREFCLK1 pin would require the pin swapping.
Also, if the GTHE3_CHANNEL is placed in a different clock region from the I/O package pins, then the appropriate GTNORTHREFCLKx pin should be used. (UG576) will have more information on the expected connectivity. Below is an image of a path that would not need the pin swapping involving the MGTREFCLK0_* package_pin, IBUFDS0_GTE3 buffer, and the GTREFCLK0 GTHE3_CHANNEL pin. In this case, The GTHE3_CHANNEL is placed in the same clock region as the I/O package pins.