We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67747

Vivado - 2016.2 - GT REFCLK pin swapping leads to partially routed nets


Using the available pin swapping feature from Vivado in an UltraScale Design results in some nets being partially routed.

In some cases, the GUI will show zero under the "Failed Routes" column from the Design Runs tab. 

However, opening the Implemented design and running the report_route_status command will show the conflicts.

Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
   # of logical nets.......................... :      231595 :
       # of nets not needing routing.......... :       78400 :
           # of internally routed nets........ :       77261 :
           # of nets with no loads............ :        1139 :
       # of routable nets..................... :      153195 :
           # of fully routed nets............. :      153192 :
       # of nets with routing errors.......... :           3 :
           # of nets with some unrouted pins.. :           1 :
           # of nets with resource conflicts.. :           3 :
   ------------------------------------------- : ----------- :

Nets with Routing Errors:
 Nets with Routing Errors:

How can I work around this?


This issue can be caused by a portion of a synthesized design having placement information (XDEF) for GT elements. 

The GTs are contained within a DCP which is added to the full project. In the full project, I/O port constraints conflict with the original GT constraints. The problem is that both the old and new GT (CHANNEL) locations are kept, which causes the routing to fail.

Vivado 2016.3 has been fixed to ignore the original constraints with the following messaging:

Reading XDEF placement.
Reading placer database...
CRITICAL WARNING: [Constraints 18-4867] Instance hierarchical_path.GTHE3_CHANNEL_PRIM_INST was already placed at GTHE3_CHANNEL_X0Y11, restoration for site GTHE3_CHANNEL_X0Y8 will be ignored.

There are a number of options for working around this issue when using Vivado 2016.2:

  1. Remove the GTHE3_CHANNEL LOC constraints from the original DCP/EDIF netlist.
  2. Avoid the need to pin swap by using the GT REFCLK clocking dedicated paths. Below are two examples:
    • Change the logical connectivity at the GTHE3_CHANNEL pin. If the input is connected to the GTREFCLK0 pin, but is using the MGTREFCLK1P package pin, then the RTL can be adjusted so that the GTREFCLK1 is used instead.
    • Change the I/O package pin constraints so that the package pin value matches the GTHE3_CHANNEL pin value.

For example, the package pin constraints for a REFCLK will either be MGTREFCLK0P or MGTREFCLK1P. If the package pin with the '1' distinction is used, then this must connect to the IBUFDS1_GTE3, and GTREFCLK1 pin of the GTHE3_CHANNEL primitive.

Using the MGTREFCLK0P and GTREFCLK1 pin would require pin swapping.

Also, if the GTHE3_CHANNEL is placed in a different clock region from the I/O package pins, then the appropriate GTNORTHREFCLKx pin should be used. (UG576) will have more information on the expected connectivity.

Below is an image of a path that would not need the pin swapping involving the MGTREFCLK0_* package_pin, IBUFDS0_GTE3 buffer, and the GTREFCLK0 GTHE3_CHANNEL pin.

In this case, The GTHE3_CHANNEL is placed in the same clock region as the I/O package pins.


AR# 67747
Date 03/15/2017
Status Active
Type General Article
  • Vivado Design Suite - 2016.2
Page Bookmarked