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AR# 67751

Vivado 2016.1: 7 Series LVCMOS18 Output Does Not Drive High as Expected


In Vivado 2016.1 some users have observed that some LVCMOS18 outputs do not drive high as expected.

If the design has been migrated from Vivado 2015.4 or earlier and the bitstream has been created in Vivado 2016.1, then LVCMOS18 outputs that previous worked might exhibit incorrect drive high behavior.

This problem occurs when the LVCMOS18 output is in a partially bonded out HR bank.

This only applies to LVCMOS18, LVCMOS25 and LVCMOS33 can drive high as expected.


For this problem to occur the following conditions need to be present:


  • The device family needs to 7 Series.
  • The output needs to be configured as LVCMOS18.
  • The output needs to be placed in a partially bonded HR bank.
  • The bitstream needs to have been created with Vivado 2016.1


The work-around is to set the below parameter before running write_bitstream:

set_param bitgen.EvalUnusedTiles true

This issue has been fixed in Vivado 2016.2.

AR# 67751
Date 09/12/2016
Status Active
Type Known Issues
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2016.1
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