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AR# 67824

2016.2 Virtex UltraScale+ - Clock Placer can fail to partition UltraScale+ designs due to not properly accounting for PS8 blocks interference with clock routing

Description

My design is failing because the clock placer fails to properly partition (floorplan) an UltraScale+ design, leading to the following Critical Warning and eventual Error:

[Place 30-891] The clock root for clock net "clock_net" needs to be in clock region X0Y3 for best timing, however, this is not possible because some of the clock loads are locked/constrained to one or more clock regions in X0Y0:X3Y2. Clock region placer will choose a different region as the clock root. Please remove any user constraint on the clock loads in the above regions to resolve this issue.

[Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net zynq_axi_i/zynq_axi_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg_0 in its partition defined by a rectangle from clock region X0Y0 to clock region X3Y3. A clock partition is a rectangular area covering all clock loads and the clock region for its clock root. It may cover the clock source as well. Each clock net needs to use the same routing track across all clock regions of its partition. In this case, other clock nets are already using resources in one or more clock regions of this partition.
Number of clock sources in each region:

Solution

This issue occurs because the clock placer is not properly accounting for the clock routing restrictions around the PS8 blocks. It can be avoided by either assigning clock roots or floorplanning loads so that clock signals do not pass through PS8 blocks.

It is planned that in a future release the automatic clock partitioning will handle this routing restriction properly.

Work-around:

Consider a PS8 block whose clock region in column 0 is X0Y0, which blocks the clock routing for a clock route assigned the clock root X0Y5 by the placer.

This conflict can be resolved in one of two ways:

1) Move the clock root to another column:

set_property USER_CLOCK_ROOT {X1Y3} [get_nets {clock_name}]

2) Floorplan the clock domain so that it does not have any loads that would cause the clock to route across the row where the PS8 block resides. 

The following constraints create a pblock which constrains all of the loads for clock net "clock_net" to clock regions above the clock region row 0:

create_pblock {CLKAG_clock_net}
add_cells_to_pblock [get_pblocks {CLKAG_clock_net}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clock_net"}]]]
resize_pblock [get_pblocks {CLKAG_clock_net}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X2Y1:CLOCKREGION_X2Y1 CLOCKREGION_X2Y2:CLOCKREGION_X2Y2 CLOCKREGION_X2Y3:CLOCKREGION_X2Y3 CLOCKREGION_X2Y4:CLOCKREGION_X2Y4 CLOCKREGION_X3Y1:CLOCKREGION_X3Y1 CLOCKREGION_X3Y2:CLOCKREGION_X3Y2 CLOCKREGION_X3Y3:CLOCKREGION_X3Y3 CLOCKREGION_X3Y4:CLOCKREGION_X3Y4 CLOCKREGION_X4Y1:CLOCKREGION_X4Y1 CLOCKREGION_X4Y2:CLOCKREGION_X4Y2 CLOCKREGION_X4Y3:CLOCKREGION_X4Y3 CLOCKREGION_X4Y4:CLOCKREGION_X4Y4 CLOCKREGION_X5Y1:CLOCKREGION_X5Y1 CLOCKREGION_X5Y2:CLOCKREGION_X5Y2 CLOCKREGION_X5Y3:CLOCKREGION_X5Y3
CLOCKREGION_X5Y4:CLOCKREGION_X5Y4}
AR# 67824
Date Created 09/06/2016
Last Updated 11/01/2016
Status Active
Type General Article
Devices
  • Virtex UltraScale+
Tools
  • Vivado Design Suite - 2016.2