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AR# 67842: 10G Ethernet Subsystem IP example design simulation running at 10.309Ghz not 10.3125Ghz
10G Ethernet Subsystem IP example design simulation running at 10.309Ghz not 10.3125Ghz
When I measure the line rate of the simulated example design the result is a line rate of 10.309GHz instead of the expected 10.3125GHz.
The comments in the simulation file give the following explanation.
`timescale 1ps / 1ps `define FRAME_TYP [32*32+32*4+16:1] // Define the refclk period in ps - in reality this should be 6400 ps = 66*96.969696.. // but that is not possible to model accurately, so use the next closest number... `define BITPERIOD 98 // Closest even number above 96.969696.. `define PERIODCORECLK 66*98 // this is the clock for 156.25MHz based on bit period of 98ps
The comments are correct and this is expected behavior.