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AR# 67858

LogiCORE Digital Pre-Distortion (DPD) v7.1 rev2 or rev3 - DPD example design does not simulate correctly


The Digital Pre-Distortion (DPD) example design does not simulate correctly when I generate a DPD core after adding the DPD v7.1 rev3 or DPD v7.1 rev2 repositories.

In a new example project, I select "run behavioral simulation" and Invoke "run -all", then wait for 10 minutes. 

Simulation runs continuously, and I see the following:

m_axis_dout_tvalid = 0, m_axid_dout_tdata = 0


This is known issue with the LogiCORE Digital Pre-Distortion (DPD) core v7.1 rev2 and rev3.

When the project settings have the target language set to VHDL, and the simulator language is set to VHDL, the example design does not run properly. 

After the example design is launched, invoking "run behavioral simulation; run -all" leads to the example design simulation running indefinitely, and giving all zeroes for the output. 

The dout_tvalid port remains at 0 and Simulation remains stuck at this stage.


To work around this issue, set the project language to Verilog and the simulator language to "mixed".

With these settings the example design runs properly and completes with a success message.

AR# 67858
Date 09/16/2016
Status Active
Type General Article
  • Digital Pre-Distortion (DPD)
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