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AR# 67859

UltraScale/UltraScale+ IDELAY/ODELAY - Problem with small initial DELAY_VALUE


For both IDELAY and ODELAY in both Native and Component mode, when using TIME mode if there is a small initial DELAY_VALUE* that is set then in hardware, the delay will not be observed as requested.

*Note: this is called RX_DELAY_VALUE and TX_DELAY_VALUE in Native mode.


In Vivado 2016.3 a software change has been made so that any DELAY_VALUE (expect 0 for the TX_BITSLICE, See (Xilinx Answer Record 66434)) can be used. However DELAY_VALUE settings of < 20ps may still have a small round off error of upto +/-15ps.

For users of 2016.2 and earlier versions, if the initial DELAY_VALUE was equal to or greater than 20 ps then this is not an issue.

For users of 2016.2 with an initial DELAY_VALUE of less than 20 ps, the delay in hardware will not be what was requested. However all of the IDELAY/ODELAYs with bytes/banks that have the same DELAY_VALUE will be aligned to each other. 

If you are using the Clock Forward feature of the High Speed SelectIO Wizard with the Phase set to 90 the clock to data alignemnet could be affected, there is an issue that due to incorrect delay on the data it will not be 90 degrees out of phase with the clock.

To work around the issue, choose an initial DELAY_VALUE equal to or greater than 20 ps.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
66434 High Speed SelectIO Wizard - Transmit interfaces may have TX_BITSLICE[0] out of alignment within each nibble N/A N/A
AR# 67859
Date 10/13/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
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  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
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