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AR# 67861

Design Advisory for Zynq UltraScale+ MPSoC Processing System - How do I upgrade from Vivado 2016.2 and earlier versions?

Description

Due to improved DRC and GUI requirements, upgrading the Zynq UltraScale+ IP from versions before Vivado 2016.3 might clear some settings from the IP configuration GUI, requiring reentry. 

The following Critical Warnings will occur if the upgrade fails:

WARNING: [PSU-1] Zynq Ultrascale Plus IP has gone through a major version revision. The upgrade process may fail with validation failures. Please refer to Section 6 (Customization Warning) in upgrade log for the validation failures. Fix the validation failures reported, in the previous version before trying upgrade again. Refer to AR#67861 for upgrade related problems.

WARNING: [IP_Flow 19-1721] During upgrade of 'design_1_zynq_ultra_ps_e_0_0':
The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.

CRITICAL WARNING: [IP_Flow 19-3408] Upgrade of design_1_zynq_ultra_ps_e_0_0 from ZYNQ UltraScale+ MPSoc 1.2 to ZYNQ UltraScale+ MPSoc 2.0 has resulted in an incomplete parameterization. Please review the message log, and recustomize this instance before continuing with your design.

CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'IP design_1_zynq_ultra_ps_e_0_0' has identified issues that may require user intervention. Please review the upgrade log /project_1/ip_upgrade.log', and verify that the upgraded IP is correctly configured.

Solution

Check all settings in the Zynq UltraScale Plus configuration GUI against the earlier Vivado version, and reenter if necessary.

Section 6 of the ip_upgrade.log referred to in the Critical Warning lists failed parameters, and might assist in determining which peripheral and function are affected.

After you confirm that the settings of the peripheral (configuration, MIO, and clocking settings) are correct, the upgrade is complete.

The following examples show some possible upgrade warnings:

Example ip_upgrade.log #1:

The following messages exists in section 6 of the Zynq UltraScale+ MPSoC Processing System IP log:

Upgrade Log for IP 'design_1_zynq_ultra_ps_e_0_0'

6. Customization warnings

-------------------------

Validation failed for parameter 'I2C0 REF CTRL DIVISOR1(PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1)' with value '1' for BD Cell 'zynq_axi_zynq_ultra_ps_e_0_0'. Error: 111.111 MHz is out of range for the parameter: PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ. Valid input frequency range is [0 : 100] MHz

Validation failed for parameter 'I2C0 REF CTRL DIVISOR0(PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0)' with value '9' for BD Cell 'zynq_axi_zynq_ultra_ps_e_0_0'. Error: 111.111 MHz is out of range for the parameter: PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ. Valid input frequency range is [0 : 100] MHz

To resolve this issue, check and update the clock settings for the I2C_0 instance. 

In general, if there are errors related to clocking during an upgrade, the appropriate divisor needs to be increased to bring the frequency within the range.

Example ip_upgrade.log #2:

Upgrade Log for IP 'design_1_zynq_ultra_ps_e_0_0'

6. Customization warnings

-------------------------

Validation failed for parameter 'SD1 IO(PSU_SD1PERIPHERALIO)' with value 'MIO 46 .. 51(4Bit)' for BD Cell 'system_zusp_ps_0'. PARAM PSUSD1PERIPHERAL_IO :: MIO 46 .. 51(4Bit) is out of range

{ EMIO,MIO 39 .. 51 }

To resolve this issue, reenter the SD_1 controller in the I/O Configuration tab to use new values for eMMC or SD modes.

AR# 67861
Date Created 09/13/2016
Last Updated 10/13/2016
Status Active
Type Design Advisory
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.3