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AR# 67885

UltraScale / UltraScale+ - How to reduce skew between the CLK - CLKDIV of the OSERDES and CLK and CLK - CLK_B of the IDDR

Description

(Xilinx Answer 68169) is a Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs which details the new minimum production speed specification version (Speed File) required for all designs.

If you have run timing with the new speed files and have skew violations between the OSERDES CLK and CLKDIV or IDDR CLK and CLK_B, the next steps to help resolve the skew violations are documented in this Answer Record.

Solution

Several solutions are available:

  • Recommended solution: migrate your project to Vivado 2016.4, update the clocking topology to the recommended topology described in this Answer Record and run the normal synthesis and implementation flow.
    • Vivado 2016.4 automatically reports the skew checks on the OSERDES and IDDR in the Timing Analysis.
  • Second solution: After updating the clocking topology, continue using an older Vivado release for your project, including for running synthesis and implementation.
    Use the Tcl script (reportIOSERDES.tcl) attached to this Answer Record to report the skew checks on the OSERDES and IDDR.
    Use Vivado 2016.4 to run timing signoff (report_timing_summary) on the routed DCP and fix any remaining skew violations (see (Xilinx Answer 68266)).
  • Third solution: After updating the clocking topology, continue using an older Vivado release with the corresponding speed files patch (limited to certain Vivado releases, available upon request), including for running synthesis and implementation.
    Use the Tcl script (reportIOSERDES.tcl) attached to this Answer Record to report the skew checks on the OSERDES and IDDR.


OSERDES CLK to CLKDIV skew

The optimal clocking topology for OSERDESE3 is shown in the diagram below. 

CLKOUT of the MMCME3 should drive two BUFGCE_DIVs in parallel, using the divide capability of one of the BUFGCE_DIVs to create the slower CLKDIV.

Note that it is not absolutely required that the global buffer driving the High-Speed Clock (CLK) be a BUFGCE_DIV cell. It can be a BUFGCE if you have a shortage of BUFGCE_DIVs.

When using multiple outputs from the MMCME3 to create the CLK and CLKDIV, check to make sure the skew requirements are met.



Fig : Recommended clocking topology

Please realize that because the BUFGCE_DIV is using a higher frequency clock that is being divided down.

As such, fabric logic must be driven with the BUFGCE_DIV as shown in Fig: Fabric Clocking With BUFGCE_DIV.


 

Fig: Fabric Clocking with BUFGCE_DIV

As shown in Fig: BUFGCE_DIV alignement,, with BUFGCE_DIVIDE = 2 or 4 the counters might start at different times. 

CLK_DIV2 A and CLK_DIV2 B show the two alignments when dividing by 2. Similarly, CLK_DIV4 A/B/C/D shows the 4 alignments that are possible when dividing by 4. 

By using the CLR and CE inputs, the counters can be aligned to a given clock edge.



Fig: BUFGCE_DIV alignment



Alternatively if you require the MMCM outputs to be phase aligned (that is CLKOUTx_PHASE) and cannot apply the correctcontrols and control the timings from Fig: BUFGCE_DIV alignment, you can use aseparate BUFG clock buffer for fabric connections.

In Fig: Fabric Clocking With MMCM clock outputs uses 3 MMCM output. CLKOUT0 drives fabric logic, another MMCM CLKOUT1 to drive the OSERDES CLKDIV and another MMCM CLKOUT2 to drive the OSERDES CLK. 

CLK and CLKDIV ports for the OSERDES are driven by BUFG's that are only connected to the OSERDES and will have similar loading/routing. CLKOUT1 and CLKOUT2 could also be used for other component primitives (ISERDES, IDELAY, ODELAY, IDELAYCTRL) as long as the routing destinations are similar.


 

Fig: Fabric Clocking With MMCM clock outputs


In Fig: Fabric Clocking With MMCM clock outputs the clock output divide settings will be a ratio of DATA_WIDTH, such that:

    CLKOUT0_DIVIDE_F = CLKOUT2_DIVIDE * DATA_WIDTH / 2

    CLKOUT1_DIVIDE = CLKOUT2_DIVIDE * DATA_WIDTH / 2

Because the outputs are coming from the MMCM, the MMCM will only lock when a given phase shift is achieved, in this case as defined by CLKOUT_<2,1,0>_PHASE.


CLOCK_DELAY_GROUP

If the design still fails to meet the requirement, the next step is to try to reduce the skew between the CLK and CLKDIV pins by assigning a CLOCK_DELAY_GROUP to the nets.

This tells the Vivado Implementation tools to balance the two clock networks. An example of the CLOCK_DELAY_GROUP is below:

set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins BUFGCE_DIV_clk_inst/O]]
set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins BUFGCE_DIV_clkdiv_inst/O]]


USER_CLOCK_ROOT

In addition to the CLOCK_DELAY_GROUP property, you can use the USER_CLOCK_ROOT property to force the clock root location of a clock driven by a clock buffer. See the below example of the USER_CLOCK_ROOT:

set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins BUFGCE_DIV_clk_inst/O]]
set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins BUFGCE_DIV_clkdiv_inst/O]]


ISERDES CLK to CLKDIV skew:

There is no skew requirement for the ISERDES CLK and CLKDIV but the recommended clocking topology would be the same as for the OSERDES.  

Use one MMCM CLKOUT driving two BUFGCE_DIVs in parallel, using the divide capability of one of the BUFGCE_DIV to create the slower CLKDIV.


IDDRE1 C to CB and ISERDES CLK to CLK_B skew 

The optimal clocking topology for the IDDR (and ISERDES) CLK and CLK_B is to use the same net to drive both pins and use local inversion to create the inverted clock. See the diagram below for an example.

See (Xilinx Answer 68331) for details on the skew check in Vivado Timing which causes an issue with skew checks on exclusive clock group constraints.



Attachments

Associated Attachments

Name File Size File Type
reportIOSERDES.tcl 17 KB TCL

Linked Answer Records

Master Answer Records

AR# 67885
Date 07/07/2017
Status Active
Type General Article
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