Version Found: DDR4 IP v2.0 (Rev. 1) and DDR3 IP v1.2 (Rev. 1)
Version Resolved: See (Xilinx Answer 58435)
Ping-Pong PHY simulations can fail when both Channels drive the CAS command in the same clock cycle but with different Slots (refer to (PG150) for more details on Ping-Pong PHY usage).
When this condition occurs, the data_in_valid signal does not assert/deassert correctly which results in read data errors.
This is a problem with the Bus Functional Model (BFM) and can be worked around by using the UNISIM simulation mode under the "Advanced" tab of the IP GUI.
09/19/2016 - Initial Release