AR# 67891

UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode

Description

Version Found: DDR4 v2.0 (Rev. 1), DDR3 v1.2 (Rev. 1)

Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036) for DDR3.

Ping-Pong PHY simulations can fail when both Channels drive the CAS command in the same clock cycle but with different Slots (refer to (PG150) for more details on Ping-Pong PHY usage).

When this condition occurs, the data_in_valid signal does not assert/deassert correctly which results in read data errors.

Solution

This is a problem with the Bus Functional Model (BFM) and can be worked around by using the UNISIM simulation mode under the "Advanced" tab of the IP GUI.


 

Revision History:

09/19/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67891
Date 01/02/2018
Status Active
Type Known Issues
Devices
Tools
IP