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AR# 67906

Vivado_timing: generated clock for the forwarded clock refers to wrong master clock

Description

In my design, two MMCM generated clocks (clk400 and clk480 respectively) feed to a BUFGMUX.

"set_case_analysis" is applied to have the multiplexer propagate clk480.

The BUFGMUX output clocks output data and also drives ODDR to forward an output clock.

I expect clk480 to be used in set_output_delay analysis but this is not the case. The tool always takes clk400 as a reference clock.

Constraints example:

set_case_analysis 0 [get_pins BUFGMUX_clk/S]
create_generated_clock -name lvds_clk -source [get_pins U_lvds_out_x8/inst/clk_fwd/CLK] -multiply_by 1 [get_ports clkout_p]

Solution

If you use the following command it does return clk480:

get_clocks -of [get_pins U_lvds_out_x8/inst/clk_fwd/CLK] 

However, if you run report_clocks you will see that the MASTER CLOCK of lvds_clk is clk400 and not clk480.

Generated Clock : lvds_clk
Master Source : U_lvds_out_x8/inst/clk_fwd/CLK
Master Clock : clk400
Multiply By : 1
Generated Sources : {clkout_p}

The master clock used for the forwarded clock is clk400 which is not the clock that propagates to the ODDR.

Workaround: Specify master_clock in the generated clock constraint.

create_generated_clock -name lvds_clk -add -master_clock clk480 -source [get_pins U_lvds_out_x8/inst/clk_fwd/CLK] -multiply_by 1 [get_ports clkout_p]

The issue is scheduled to be fixed in a future Vivado release.

AR# 67906
Date Created 09/21/2016
Last Updated 11/03/2016
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.1
  • More
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
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