In my design, two MMCM generated clocks (clk400 and clk480 respectively) feed to a BUFGMUX.
"set_case_analysis" is applied to have the multiplexer propagate clk480.
The BUFGMUX output clocks output data as well as drives ODDR to forward an output clock.
I expect clk480 to be used in set_output_delay analysis but this is not the case. The tool always takes clk400 as a reference clock.
If you use the following command it does return clk480:
get_clocks -of [get_pins U_lvds_out_x8/inst/clk_fwd/CLK]
However, if you run report_clocks you will see that the MASTER CLOCK of lvds_clk is clk400 and not clk480.
The master clock used for the forwarded clock is clk400 which is not the clock that propagates to the ODDR.
Work-around: Specify master_clock in the generated clock constraint.
The issue has been fixed in Vivado 2017.1 and later versions.