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AR# 67919

UltraScale - OBUFDS_GTE3/4 output is not toggling

Description

For some protocols, the OBUFDS_GTE3/4 needs to be instantiated manually. 

The differential clock output is not toggling after I instantiate OBUFDS_GTE3/4 via the language template.

However, the clock behavior is correct in simulation.

Why is this occurring?

Solution

To resolve this issue, modify the REFCLK_ICNTL_TX(5'b00000) into REFCLK_ICNTL_TX(5'b00111) as the transceiver wizard recommends:

//  <-----Cut code below this line---->

   // OBUFDS_GTE4: Gigabit Transceiver Buffer
   //              Virtex UltraScale+
   // Xilinx HDL Language Template, version 2016.2

   OBUFDS_GTE4 #(
      .REFCLK_EN_TX_PATH(1'b1),   // Refer to Transceiver User Guide
      .REFCLK_ICNTL_TX(5'b00000)  // Refer to Transceiver User Guide
   )
   OBUFDS_GTE4_inst (
      .O(O),     // 1-bit output: Refer to Transceiver User Guide
      .OB(OB),   // 1-bit output: Refer to Transceiver User Guide
      .CEB(CEB), // 1-bit input: Refer to Transceiver User Guide
      .I(I)      // 1-bit input: Refer to Transceiver User Guide
   );

   // End of OBUFDS_GTE4_inst instantiation
AR# 67919
Date Created 09/23/2016
Last Updated 10/20/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale+
  • Kintex UltraScale
  • Virtex UltraScale+
  • Virtex UltraScale
Tools
  • Vivado Design Suite