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AR# 67933

UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.

Description

Version Found: v2.1

Version Resolved: See (Xilinx Answer 58435)

When a project containing Memory IP configured with a custom part is archived, moved, and then un-archived, the example design generated for the IP from the un-archived project fails during synthesis with the below errors:

ERROR: [Synth 8-439] module 'my_mig_phy' not found [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj/my_mig_ex
/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3_mem_intfc.sv:595]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig_ddr3_mem_intfc' [/proj/dsv_xhd/pparata/ddr3_arch
/ex_proj/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3_mem_intfc.sv:70]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig_ddr3' [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj
/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3.sv:153]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig' [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj
/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig.sv:73]

Solution

There are two available work-arounds for the issue:

 

  • Close and reopen the example project
  • Regenerate the Memory IP in the example project

 

Revision History:

09/26/2016 - Initial Release

AR# 67933
Date Created 09/26/2016
Last Updated 11/02/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale