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AR# 67943

Vivado Synthesis - "black_box = false" does not work

Description

When I set a black_box attribute to False or No in the VHDL RTL, it is always taken as True or Yes by Vivado Synthesis.

Example code:

architecture am_err_cntr_arch of am_err_cntr is

  attribute black_box : string;
  attribute black_box of am_err_cntr_arch : architecture is "NO";

  signal compx96   : std_logic_vector(95 downto 0 ) := (others => '0');
  ......
begin
  compx96 <= data xor ref_val;
  ......
end am_err_cntr_arch;

In the synthesized netlist, "am_err_cntr" is a black box despite what I have set.

Solution

The black_box attribute is used to make something a black box. The default value is "false".

If you do not want it to be a black box, just remove the attribute from the RTL.

Explicitly setting it to False or No in RTL is not supported.

AR# 67943
Date Created 09/27/2016
Last Updated 10/13/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite