UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67946

Vivado Synthesis - Using VHDL configuration without the component instantiation statement is not supported

Description

When I use a VHDL configuration similar to the following, Vivado Synthesis returns an error.

Example code:

architecture arch of top is
begin
  U : configuration work.mycfg port map (
                                        din => din,
                                        dout => dout
                                      );
end arch;

Error message:

ERROR: [Synth 8-5826] no such design unit 'mycfg' in library 'work' [xxxxxx/top.vhd:31].

Solution

Using a VHDL configuration without the component instantiation statement is not supported.

The supported coding style is as follows:


architecture arch of top is
component cfg_comp 
  port (
        din : in std_logic_vector(1 downto 0);
        dout : out std_logic_vector(1 downto 0)
       );
end component;      
for U : cfg_comp use configuration work.mycfg;              

begin
  U : cfg_comp port map (
                                        din => din,
                                        dout => dout
                                      );
end arch;


The complete code example is attached in this Answer Record.

Attachments

Associated Attachments

Name File Size File Type
67946_code_example.zip 1 KB ZIP
AR# 67946
Date Created 09/27/2016
Last Updated 10/13/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite