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AR# 67947

Vivado Synthesis - XDC read in before a second synth_design run is not used by Synthesis in non-project mode Tcl script flow

Description

I have a Tcl script similar to the following:

source src/run.files
synth_design -top top -part xcvu065-ffvc1517-3-e-es2 
write_verilog -force top_out.v
report_timing -file timing.rpt

read_xdc src/top.xdc
synth_design -top top -part xcvu065-ffvc1517-3-e-es2
write_verilog -force ret_top_out.v
report_timing -file ret_timing.rpt

The second synth_design run does not use the XDC. What is the cause of this problem?

Solution

This is expected behavior.

The synth_design command synthesizes the design and puts it in memory. The second synth_design command is actually synthesizing the already opened design.

If you wish to add a new source and re-synthesize the design, you will need to close the project and start over from the beginning.

source src/run.files
synth_design -top top -part xcvu065-ffvc1517-3-e-es2 
write_verilog -force top_out.v
report_timing -file timing.rpt

close_project

source src/run.files

read_xdc src/top.xdc
synth_design -top top -part xcvu065-ffvc1517-3-e-es2
write_verilog -force ret_top_out.v
report_timing -file ret_timing.rpt

AR# 67947
Date Created 09/27/2016
Last Updated 10/13/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite