Vivado Synthesis interprets @(negedge clk) as a LUT-inverter connected to the clock pin of the register.
This causes the following DRC warning if I report DRC in the Synthesized design.
How can I resolve this issue?
This issue has been fixed in Vivado 2017.1.
In earlier versions, this post-synthesis DRC warning can be ignored as the LUT-inverter on the clock net will be pushed into the register cell to use the local inverter in it during opt_design.