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AR# 67948

Vivado Synthesis - Post-Synthesis DRC Warning PLHOLDVIO #1: A LUT <LUT_cell_name> is driving clock pin of n cells


Vivado Synthesis interprets @(negedge clk) as a LUT-inverter connected to the clock pin of the register.

This causes the following DRC warning if I report DRC in the Synthesized design.

A LUT <LUT_cell_name> is driving clock pin of n cells. This could lead to large hold time violations.
First few involved cells are:
  <FF_cell_name> {FDRE}

How can I resolve this issue?


This issue has been fixed in Vivado 2017.1.

In earlier versions, this post-synthesis DRC warning can be ignored as the LUT-inverter on the clock net will be pushed into the register cell to use the local inverter in it during opt_design.

AR# 67948
Date 04/19/2017
Status Active
Type General Article
  • Vivado Design Suite