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AR# 67957

UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP

Description

Version Found: DDR4/3 v2.1; RLD3 v1.3, QDRII+ v1.3; QDRIV v1.2

Version Resolved: See (Xilinx Answer 58435)

When opening a Vivado project in 2016.3 that was created with an older Vivado version, implementation will fail with the following error if the Memory IP is not upgraded:

[Mig 66-119] Phy core regeneration & stitching failed. Please check vivado.log and debug_core_synth.log files in the directory

Solution

The PHY IP is required to be updated in each Vivado release. If the full IP cannot be upgraded, please open a Service Request.

Release History:

10/05/2016 - Initial Release

AR# 67957
Date Created 09/27/2016
Last Updated 10/13/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
IP
  • MIG UltraScale