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AR# 67969

Xilinx Hybrid Memory Cube (XHMC) IP for UltraScale and UltraScale+ - IP Release Notes and Known Issues for Vivado 2016.3 and newer tool versions


This answer record contains the Release Notes and Known Issues for the XHMC IP Cores and includes the following:

  • Supported Devices
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.3 and newer tool versions.




General Information

Supported FPGA devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

XHMC IP Core VersionVivado Tools Version
V1.0 (Rev. 5)2017.4
V1.0 (Rev. 4)
V1.0 (Rev. 3)
v1.0 (Rev. 2)2017.1
v1.0 (Rev. 1)2016.4

For an overview of the Core Architecture and Product Specification for UltraScale FPGAs, see the LogiCORE IP Product Guide for XHMC v1.0 (PG216) located at:


For a complete list of supported HMC devices please refer to Table 2.

Table 2: HMC device support


For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:


For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

The following table provides known issues for the XHMC IP and UltraScale and UltraScale+, starting with v1.0, initially released in the Vivado 2016.3 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 70235)XHMC IP - Simulations Show Low Performance with Micron BFM V1.0Not a Bug
(Xilinx Answer 70180)XHMC IP - AXI RID Port Width Mismatch from Top Level to Internal DesignV1.0 (Rev. 4)
Not Resolved
(Xilinx Answer 70056) XHMC IP - Debug Nets not Automatically Added to a Debug Hub then Generating the Example DesignV1.0 (Rev. 1)Not Resolved
(Xilinx Answer 70032)XHMC IP - GTH Port Width Mismatches for DRP Address and IBERT ConfigurationV1.0 (Rev. 3)
Not Resolved
(Xilinx Answer 69226)XHMC IP - Clear Error Abort Flag (FRP[1]) not being Set in IRTRY PacketsV1.0 (Rev. 1)
V1.0 (Rev. 3)
(Xilinx Answer 67974)XHMC IP - Vivado Simulator does not support Micron HMC BFMv1.0V1.0 (Rev. 3)
(Xilinx Answer 68421)XHMC IP - Invalid FLIT Width Selectable for AXI4MM Write and Read Data Widthsv1.0v1.0 (Rev. 2)
(Xilinx Answer 68217)XHMC IP - AXI axi4mm_wready does not propagate backpressure correctlyv1.0v1.0 (Rev. 1)
(Xilinx Answer 68085)XHMC IP - VCU110 requires that "GT Insertion Loss at Nyquist" be equal to 4v1.0v1.0 (Rev. 1)
(Xilinx Answer 68074)XHMC IP - VCU110 does not support half-width configurationv1.0v1.0 (Rev. 1)
(Xilinx Answer 67973)XHMC IP - Timing Failures May Occur During Implementationv1.0Not Resolved

Revision History:

10/05/2016Initial Release
10/14/2016Added AR68074
10/17/2016Added AR68085
12/19/2016Updated for 2016.4 Release
03/16/2017Updated for 2017.1 Release
06/01/2017Updated for AR69226
06/05/2017Updated for 2017.2 Release
09/15/2017Updated for 2017.3 Release
11/02/2017Added AR70032 and AR70056
11/27/2017Added AR70180
12/07/2017Added AR70235 and updated for 2017.4

Linked Answer Records

Child Answer Records

AR# 67969
Date 12/20/2017
Status Active
Type Release Notes
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale+
  • Vivado Design Suite
  • MIG UltraScale
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