This answer record contains the Release Notes and Known Issues for the XHMC IP Cores and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.3 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
XHMC IP Page:
Supported FPGA devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|XHMC IP Core Version||Vivado Tools Version|
|v1.0 (Rev. 1)||2016.4|
For an overview of the Core Architecture and Product Specification for UltraScale FPGAs, see the LogiCORE IP Product Guide for XHMC v1.0 (PG216) located at:
For a complete list of supported HMC devices please refer to Table 2.
Table 2: HMC device support
For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.
For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Known and Resolved Issues
The following table provides known issues for the XHMC IP and UltraScale and UltraScale+, starting with v1.0, initially released in the Vivado 2016.3 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 68421)||XHMC IP - Invalid FLIT Width Selectable for AXI4MM Write and Read Data Widths||v1.0||Not Resolved|
|(Xilinx Answer 67974)||XHMC IP - Vivado Simulator does not support Micron HMC BFM||v1.0||Not Resolved|
|(Xilinx Answer 68217)||XHMC IP - AXI axi4mm_wready does not propagate backpressure correctly||v1.0||v1.0 (Rev. 1)|
|(Xilinx Answer 68085)||XHMC IP - VCU110 requires that "GT Insertion Loss at Nyquist" be equal to 4||v1.0||v1.0 (Rev. 1)|
|(Xilinx Answer 68074)||XHMC IP - VCU110 does not support half-width configuration||v1.0||v1.0 (Rev. 1)|
|(Xilinx Answer 67973)||XHMC IP - Timing failures may occur during implementation||v1.0||v1.0 (Rev. 1)|
|12/19/2016||Updated for 2016.4 Release|