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AR# 67969

Xilinx Hybrid Memory Cube (XHMC) IP for UltraScale and UltraScale+ - IP Release Notes and Known Issues for Vivado 2016.3 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the XHMC IP Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.3 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

XHMC IP Page:

http://www.xilinx.com/products/intellectual-property/ef-di-xhmc.html

Solution

General Information

Supported FPGA devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

XHMC IP Core VersionVivado Tools Version
v1.02016.3


For an overview of the Core Architecture and Product Specification for UltraScale FPGAs, see the LogiCORE IP Product Guide for XHMC v1.0 (PG216) located at:

http://www.xilinx.com/products/intellectual-property/ef-di-xhmc.html

For a complete list of supported HMC devices please refer to Table 2.

Table 2: HMC device support

MT43A4G40200NFA-S15
MT43A4G80200NFH-S15


For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Known and Resolved Issues

The following table provides known issues for the XHMC IP and UltraScale and UltraScale+, starting with v1.0, initially released in the Vivado 2016.3 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 68217)XHMC IP - AXI axi4mm_wready does not propagate backpressure correctlyv1.0Not Resolved
(Xilinx Answer 68085)XHMC IP - VCU110 requires that "GT Insertion Loss at Nyquist" be equal to 4v1.0Not Resolved
(Xilinx Answer 68074)XHMC IP - VCU110 does not support half-width configurationv1.0Not Resolved
(Xilinx Answer 67974)XHMC IP - Vivado Simulator does not support Micron HMC BFMv1.0Not Resolved
(Xilinx Answer 67973)XHMC IP - Timing failures may occur during implementationv1.0Not Resolved

Revision History:


10/05/2016Initial Release
10/14/2016Added AR68074
10/17/2016Added AR68085
AR# 67969
Date Created 09/28/2016
Last Updated 11/24/2016
Status Active
Type Release Notes
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale+
IP
  • MIG UltraScale