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AR# 67973

XHMC IP - Timing Failures Can Occur During Implementation

Description

Version Found: XHMC IP v1.0 for Case 1 and XHMC IP v1.0 (Rev .4) for Case 2

Version Resolved: See (Xilinx Answer 67969)

There are two cases where the XHMC IP can encounter timing failures during implementation.

Case 1:

Timing failures can occur if the recommended HMC protocol datapath width is not used. Please refer to the HMC IP User Guide for more details.

It is recommended to use the following data path width (FLITs) in the IP GUI to ensure that timing can be met in Vivado:


 

Case 2:

In some rare cases there might be timing failures along paths that include BRAMs in the XHMC design.

Solution

Case 1:

If timing still cannot be met due to routing congestion or high device utilization, you might need to use one of the following options:

  • Use a different timing closure strategy (for example, Explore)
  • Use the "-extraNetDelay_high" implementation option
  • Increase the datapath width further to ease timing closure.

Case 2:

These timing failures along paths that include BRAMs are caused by the Vivado power optimization logic paths inserted in to the design.  

This issue can be resolved by disabling the power optimization logic along the BRAM timing path.

Here is an example of excluding a failing path:

set_power_opt -exclude_cells [get_cells -hier -filter {NAME =~ *genblk_pload_mem_inst.u_resp_pload_mem/genblk_block_ram_model.the_bram_reg_*}]

Revision History:


  • 10/05/2016 - Initial Release
  • 09/15/2017 - Updated for BRAM timing path issues

Linked Answer Records

Master Answer Records

AR# 67973
Date 02/07/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
Tools
  • Vivado Design Suite
IP
  • MIG UltraScale
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