UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67975

UltraScale/UltraScale+ Interlaken - OOBFC RX input timing constraints are relaxed

Description

The Interlaken Specification calls for a 0.75ns setup and 0.75ns hold on the RX OOBFC (Out of Band Flow Control) inputs. In the .xdc constraints provided with the core, these have been relaxed:

set_input_delay -clock [get_clocks RX_FC_CLK] -max 3.80 [get_ports [list rx_fc_data rx_fc_sync]];
set_input_delay -clock [get_clocks RX_FC_CLK] -min 1.20 [get_ports [list rx_fc_data rx_fc_sync]];
set_input_delay -clock [get_clocks RX_FC_CLK] -max 3.80 [get_ports [list rx_fc_data rx_fc_sync]] -clock_fall -add_delay;
set_input_delay -clock [get_clocks RX_FC_CLK] -min 1.20 [get_ports [list rx_fc_data rx_fc_sync]] -clock_fall -add_delay;

Solution

The OOBFC clock runs at a max of 100Mhz. It is expected that in most systems the above constraints will provide plenty of skew margin for a 100Mhz or slower clock and data. 

If a smaller window is required, phase adjustments can be made to the MMCM for the specific speed grade, device and location that are being used. 

If further assistance is needed, please contact Xilinx Technical Support.

AR# 67975
Date Created 09/28/2016
Last Updated 10/13/2016
Status Active
Type General Article
IP
  • Interlaken Core