The Interlaken Specification calls for a 0.75ns setup and 0.75ns hold on the RX OOBFC (Out of Band Flow Control) inputs. In the .xdc constraints provided with the core, these have been relaxed:
The OOBFC clock runs at a max of 100Mhz. It is expected that in most systems the above constraints will provide plenty of skew margin for a 100Mhz or slower clock and data.
If a smaller window is required, phase adjustments can be made to the MMCM for the specific speed grade, device and location that are being used.
If further assistance is needed, please contact Xilinx Technical Support.