Version Found: DDR4 v2.1
Version Resolved: See (Xilinx Answer 58435)
I am targeting an FPGA device with the -1H speed grade and am using the wizard feature to "Specify MMCM M and D on Advanced Clocking Page to calculate Ref Clk reference input clock speed (ps)".
However, an error message similar to the following appears upon IP generation:
This error is generated even though the calculated MMCM VCO values are valid as per the FPGA data sheet.
This issue is specific to the "manual selection of M and D values" feature for -1H speed grade.
This is a Known Issue.
Until this issue is resolved, select a different M, D and Do combination for the Reference Input Clock Speed to avoid this error.
Alternatively, select the reference input clock speed from the drop down list in the GUI instead of using the manual M and D selection.
10/05/2016 - Initial Release