We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67979

UltraScale DDR4 - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed grade


Version Found: DDR4 v2.1

Version Resolved: See (Xilinx Answer 69035)

I am targeting an FPGA device with the -1H speed grade and am using the wizard feature to "Specify MMCM M and D on Advanced Clocking Page to calculate Ref Clk reference input clock speed (ps)".

However, an error message similar to the following appears upon IP generation:

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'C0.DDR4 CLKFBOUT MULT(C0.DDR4_CLKFBOUT_MULT)' with value '11' for IP 'SN93_virtexuDDR4'.
Using the above formulae, calculated VCO value(1232) with the given CLKFBOUT_MULT , DIVCLK_DIVIDE, CLKOUT0_DIVIDE values, doesn't fall with in the range [600,1200]

This error is generated even though the calculated MMCM VCO values are valid as per the FPGA data sheet.

This issue is specific to the "manual selection of M and D values" feature for -1H speed grade.


This is a Known Issue.

Until this issue is resolved, select a different M, D and Do combination for the Reference Input Clock Speed to avoid this error.

Alternatively, select the reference input clock speed from the drop down list in the GUI instead of using the manual M and D selection.

Revision History:

10/05/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67979
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
  • MIG UltraScale
Page Bookmarked