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AR# 68006

Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly

Description

Some designs created in the 2016.1 and 2016.2 versions of Xilinx Design Tools have been found to have incorrect bitstreams. The root cause has been identified as a multi-threading (default) issue in write_bitstream, which can cause some configuration memory cells to be set to 0 instead of 1. 

CRC will still pass for these bitstreams, as the bitstream CRC is calculated using the incorrectly set values and will result in a valid check when the bitstream is loaded. 

All devices (7 Series, Zynq-7000, UltraScale, UltraScale+, and Zynq UltraScale+) and all OS's (Windows and Linux) are impacted by this issue.

Xilinx Design Tools including Vivado, SDAccel, and SDSoC (2016.1 and 2016.2 versions) are impacted.

Multi-threading is turned off for write_bitstream in Vivado 2016.3, SDAccel 2016.3 and SDSoC 2016.3, so this issue will not occur for those versions and later.

Solution

New designs using Vivado, SDAccel or SDSoC 2016.1 or 2016.2 must be generated with the instructions below. Alternatively, you can update to Xilinx Design Tools 2016.3, where multi-threading for write_bitstream is turned off.

Instructions:

Permanently force the use of a single thread during bitstream generation with any 2016.1 or 2016.2 Xilinx Design Tool releases by adding the following Tcl command to the init.tcl script:

if {[regexp {^2016\.[12].*} [version -short]]} { set_param bitgen.maxThreads 1 }

Note: This command only sets write_bitstream to use a single thread. It does not affect other processes.


Additional information on init.tcl:

When you start the Xilinx Design tools, it looks for the init.tcl initialization script in two different locations:

1) In the software installation: installdir/Vivado/version/scripts/init.tcl

installdir is the installation directory where the Vivado Design Suite is installed.

2) In the local user directory:

  1. For Windows 7: %APPDATA%/Roaming/Xilinx/Vivado/init.tcl
  2. For Linux: $HOME/.Xilinx/Vivado/init.tcl


If init.tcl exists in both of these locations, Vivado sources the file from the installation directory first, and then from your home directory.

For more information, see the Loading and Running Tcl Scripts chapter in (UG894) Vivado Design Suite User Guide Using Tcl Scripting.

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug894-vivado-tcl-scripting.pdf


Existing bitstreams created in Vivado, SDAccel or SDSoC 2016.1 or 2016.2 can be verified for correctness by regenerating the bitstream using a single thread, and doing a comparison.

A Tcl script called AR68006.tcl is attached to this Answer Record, and can be used to regenerate the bitstream with a single thread, and do the comparison.

NOTE:  Ensure that the same Xilinx Design Tool release that was used to generate xxOLD.bit is used to run the AR68006.tcl script that generates NEW.bit
             -  Additionally, If using 2016.1 please ensure that the same OS that was used to generate xxOLD.bit is used to run the AR68006.tcl script that generates NEW.bit.

Instructions:

1) Download the attached script, 'AR68006.tcl'.

2. From the Tcl command line enter the following command:

vivado -mode batch -source AR68006.tcl -tclargs xxOLD.dcp xxOLD.bit ConfigMode elfFileName 
  • xxOLD.dcp : Specify the routed dcp of your old design that needs to be verified.
  • xxOLD.bit : Specify the bit file that was generated with xxOLD.dcp and is being used currently.
  • ConfigMode : Specify the config interface used: SMAPx8, SMAPx16, SMAPx32, SERIALx1, SPIx1, SPIx2, SPIx4, SPIx8, BPIx8, BPIx16.
  • elfFileName : Specify the ELF file name that is used. If no ELF file is used, use NONE for elfFilename
3) Review the resulting message to determine whether your existing bitstream is correct.

4) NEXT STEPS if mismatches are found between the existing bitstream and the new bitstream generated with a single thread:

a) Double check to ensure the new bitstream has been generated correctly by reviewing the following:
  • Ensure that the xxOLD.dcp used is the correctly routed DCP that was used to generate the existing bitstream
  • Apply any additional bitstream properties that were used to generate the existing bitstream as instructed in the script (note that setting the "BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP" property will cause mismatches)
b) If the above steps are reviewed and mismatches still occur, then update the existing bitstream by generating a new bitstream using the instructions for 'New Designs' above. (i.e. generate a new bitstream using a single thread by using the Tcl Command shown above or update to Xilinx Design Tools 2016.3)

5) Please contact Xilinx Technical Support with any additional questions or concerns.

Attachments

Associated Attachments

Name File Size File Type
AR68006.tcl 3 KB TCL
AR# 68006
Date Created 09/30/2016
Last Updated 10/28/2016
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Artix-7Q
  • Kintex UltraScale
  • More
  • Kintex UltraScale+
  • Kintex-7
  • Kintex-7Q
  • Virtex UltraScale
  • Virtex UltraScale+
  • XA Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq-7000
  • Zynq-7000Q
  • Less
Tools
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1
  • SDAccel
  • SDSoC