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AR# 68007

[Vivado 2016.2] ERROR: [Project 1-9] Cannot open structural netlist because no structural source files were specified. Edif, ngc ngo and verilog structural netlists are supported

Description

My design has completed Implementation successfully, but the following error message is seen when trying to open the implemented design.

ERROR: [Project 1-9] Cannot open structural netlist because no structural source files were specified. Edif, ngc ngo and verilog structural netlists are supported

This prevents me from analyzing the implementation results, for example by running timing analysis.

The below thread in the Xilinx Community forums contains a more complete description of the issue:

https://forums.xilinx.com/t5/Design-Entry/Top-module-setting-lost/td-p/510195

Solution

To work around this issue, open the routed DCP instead of the implemented design to perform the required analysis.

AR# 68007
Date Created 09/30/2016
Last Updated 11/01/2016
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite