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AR# 68021

2016.3 Vivado IP Release Notes - All IP Change Log Information Article

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2016.3 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

 

 

Solution

(c) Copyright 2016 Xilinx, Inc. All rights reserved.

 

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

 

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10G Ethernet MAC (15.1)

 

* Version 15.1 (Rev. 2)

* Bug Fix: Fix corner case RX issue - If reset is asserted in mid of frame reception then tvalid is not de-asserted

* Bug Fix: Fix corner case RX issue - If there is a cable pull event as soon as the frame starts then AXI-S tvalid may not be de-asserted

* Bug Fix: Fix RX statistics issue - Statistics vector bit 29 is wrongly asserted for padded VLAN and normal frames

* Bug Fix: Fix Example Design RX FIFO 64-bit - Read does not stop immediately when fifo_tready is deasserted soon after the last word has been read-out from FIFO

* Other: Spartan-7 Pre-Production support

* Other: Updated license information

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 6)

* Port Change: Bringing TXPD, RXPD, TXELECIDLE, TXPDELECIDLEMODE, CPLLPD, QPLL0PD and QPLL1PD pins to top

* Port Change: Bringing rxprbslocked signal to top

* Bug Fix: Fixed the issue where reference clock for GTX is using IBUF without IBUF_LOW_PWR=FALSE setting

* Feature Enhancement: Changed use of Gearbox in GT from Asynchronous to Synchronous for KR designs for UltraScale devices

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 2)

* General: Refer to ten_gig_eth_mac_v15_1 and ten_gig_eth_pcs_pma_v6_0 core change logs for changes in the sub cores of this core.

* General: Changed use of Gearbox in GT from Asynchronous to Synchronous for KR designs for UltraScale devices.

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.0)

* Version 2.0

* Port Change: New port gt_refclk_out by default and rx_ptp_tstamp_valid_out for 1588 configuration added as per request.

* Port Change: New port rx_serdes_clk_0, rx_serdes_clk_1, rx_serdes_clk_2, rx_serdes_clk_3, rx_serdes_reset_0, rx_serdes_reset_1, rx_serdes_reset_2, rx_serdes_reset_3 added for gt out of core configuration`

* Feature Enhancement: 1588 2 Step support for PCS variant

* Feature Enhancement: Added IP Integrator Designer Assistance support with block, connection and board automation

* Feature Enhancement: Added 25G support for Ultra Scale Plus -2lV speed grade devices

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.0)

* Version 16.0

* Port Change: phyaddr port added ,earlier this was a core parameter.

* Bug Fix: naming of generated clock removed from block XDC while interfacing with GEM, to avoid naming conflict in case of multiple instances of IP

* New Feature: Added support for Multi-lane Asynchronous SGMII/BASEX over LVDS for UltraScale and UltraScale+ devices

* New Feature: Added option to select GT location for UltraScale and UltraScale+ devices

* Feature Enhancement: Added support for Spartan-7 Devices.

* Feature Enhancement: Added logic to perform clock correction on C1/C2 code groups in receive elastic buffer.

* Feature Enhancement: Added option to choose from Synchronous SGMII based on component mode and Asynchronous SGMII solution based on Native mode of IO for UltraScale.

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 12)

* General: Added support for Spartan-7.  No change to functionality.

* Revision change in one or more subcores

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

40G/50G Ethernet Subsystem (2.0)

* Version 2.0

* Port Change: SerDes data and header ports added for GT in Example design

* Port Change: Ports added for 1588 1 step

* Port Change: Ports added for Runtime switchable

* Feature Enhancement: GT outside the IP

* Feature Enhancement: 40G/50G Ethernet with 50G RS-FEC and 1588 1-step

* Feature Enhancement: 40G/50G Ethernet runtime switchable for US and US plus

* Feature Enhancement: 40G board support in IP Integrator and Designer Assistance

* Feature Enhancement: 50GBASE-KR2 enable RS-FEC and KR FEC in same configuration per 50GBASE-CR specification with optional AN/LT

* Feature Enhancement: Added 50G support for UltraScale Plus -2lV speed grade devices

* Feature Enhancement: Removed support for 40G with -1 speed devices

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 4)

* Feature Enhancement: JESD204 template preset for align_comma_word updated

* Feature Enhancement: resetdones updated for JESD template based configurations

* Other: Added support for XC7A12TCSG325, XC7A25TCSG325 and XC7Z012SCLG485 devices

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 2)

* Bug Fix: Updated text in core configuration GUI to display Capabilities Register value as 0x0142 when Slot Implemented option is selected for Rootport Mode

* Other: Added support for xc7a12t,xc7a12t,xc7a25t,xc7a25ti and xc7z012s devices

* Revision change in one or more subcores

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI 1G/2.5G Ethernet Subsystem (7.0)

* Version 7.0 (Rev. 6)

* New Feature: Added support for Asynchronous SGMII/BASEX over LVDS for UltraScale and UltraScale+ devices.

* New Feature: Added option to select GT location for UltraScale and UltraScale+ devices.

* Feature Enhancement: Added option to choose from Synchronous SGMII based on component mode and Asynchronous SGMII solution based on Native mode of I/O for UltraScale.

* Other: Added support for Spartan-7 Devices.

* Other: Gig PCS/PMA subcore version updated to v16_0.

* Other: Refer to tri_mode_ethernet_mac v9.0 and gig_ethernet_pcs_pma v16_0 core change logs for changes in the sub cores of this core.

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI AMM Bridge (1.0)

* Version 1.0

* General: First Release of IP

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI BFM Cores (5.0)

* Version 5.0 (Rev. 7)

* No changes

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0

* Port Change: Added pipe_{rx/tx}_{8-15}_sigs ports to support pipe simulation in  UltraScale+ x16 configuration

* Port Change: Removed axi_ctl_aclk port for new IP creation. IP that is upgraded is not affected

* Other: Added support for FLG1155/FLG1931 packages for xc7vh580t device, FLG1931 for xc7vh870t device, FFV1156/FFV1761 for xc7vx330t device, FFV1157/FFV1158/FFV1927 for xc7vx415T device

* Other: AXIBAR_NUM, BASEADDR, and HIGHADDR parameters are now converted to upper-case to improve driver backward compatibility with AXI Memory Mapped to PCI Express for 7-series IP

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 13)

* General: No functional changes

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 10)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Chip2Chip Bridge (4.2)

* Version 4.2 (Rev. 10)

* Bug Fix: IP updated to avoid cascading of BUFGs

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 9)

* Feature Enhancement: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Feature Enhancement: Added simplified asynchronous clock crossing when in AXI4LITE

* Feature Enhancement: Updated IP clocking XDC to reduce run-time when using async CDC; clocking XDC marked as implementation-only.

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 11)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 10)

* Feature Enhancement: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Feature Enhancement: Updated IP clocking XDC to reduce run-time when using asynchronous CDC; clocking XDC marked as implementation-only.

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 12)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 11)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 10)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 13)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 13)

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 12)

* Bug Fix: Board flow related fix

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 14)

* Feature Enhancement: IP updated to support Spartan-7 device family

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 13)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 11)

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 8)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 2)

* Feature Enhancement: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Feature Enhancement: Added DRC for AXIS_CTL_SIZE for RP and EP. Updated Tooltip for BASEADDR and HIGHADDR parameters in core configuration GUI page

* Feature Enhancement: Changed default value for HIGHADDR to 0x00001FFF

* Feature Enhancement: Added Tie off for M_AXI interface.

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Fixed issue with IP Integrator address editor integration for address widths greater than 32 bits.

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 12)

* Feature Enhancement: Logic, XDC updated for better Fmax performance

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Protocol Checker (1.1)

* Version 1.1 (Rev. 11)

* Clarified description of pc_asserted[59] (AXI_ERRS_RID).

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 9)

* New Feature: IP updated to access two Quad SPI flashes connected to FPGA (example KCU105)

* Feature Enhancement: Support for Spartan-7 device family

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Improve runtime performance of IP Customization GUI. No changes required by the user

* Revision change in one or more subcores

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 2)

* Resolved various bugs.

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 14)

* Feature Enhancement: IP updated to support Spartan-7 device family

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 2)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 12)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Traffic Generator (2.0)

* Version 2.0 (Rev. 11)

* Feature Enhancement: Enhanced support for IP Integrator

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 12)

* Feature Enhancement: IP modified to support Spartan-7 device family

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 11)

* Feature Enhancement: IP updated to support Spartan-7 device family

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 14)

* Bug Fix: GUI related updates. GUI allows setting of only valid baud rate values.

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.2)

* Version 6.2 (Rev. 9)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* General: Name and location of Verilog include file changed

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 12)

* Adopted inference based memory in place of memory generator. No Impact of customer designs expected

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 7)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 11)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Update FIFO Generator constraints.

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 11)

* Updated XDC in sync with FIFO changes

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 9)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 11)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.1)

* Version 1.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 10)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 4)

* Feature Enhancement: Added 8 pixels per clock support

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user.)

* Other: Updated to use FIFO Generator v13.1

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Aurora 64B66B (11.1)

* Version 11.1 (Rev. 2)

* Feature Enhancement: Added Advanced RX GT Options selection in GUI for UltraScale devices

* Feature Enhancement: Added support for GTYE4 up to 25.7813Gbps line rates

* Feature Enhancement: Updated support for GTYE3 up to 25.7813Gbps line rates

* Revision change in one or more subcores

Aurora 8B10B (11.0)

* Version 11.0 (Rev. 6)

* Bug Fix: Fixed issue in failure due to floating point precision difference of gt_refclk in validate BD design in IP Integrator

* Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol

* Feature Enhancement: Added Advanced RX GT Options selection in GUI

* Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Block Memory Generator (8.3)

* Version 8.3 (Rev. 4)

* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled

* Other: Enable support for future devices

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

CANFD (1.0)

* Version 1.0 (Rev. 3)

* General: Spartan-7 device support added, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

CORDIC (6.0)

* Version 6.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

CPRI (8.7)

* Version 8.7

* Port Change: Routed rxrecclkout from the UltraScale transceiver up to a core output.

* Bug Fix: Fixed protocol negotiation issue where slave core would always transmit protocol version 1.

* Feature Enhancement: Implemented increased insertion loss and equalization mode settings for UltraScale devices.

* Feature Enhancement: Added 10.1376Gbps and 8B10B line rate support to 24.33024Gbps capable cores.

* Feature Enhancement: Added 245.76MHz reference clock option to 24.33024Gbps, 12.16512Gbps and 10.1376Gbps capable cores in GTYE3, GTHE4 and GTYE4 based devices.

* Feature Enhancement: Added 24.33024Gbps option to UltraScale+ GTYE4 based cores.

* Feature Enhancement: Added RS-FEC support for 64b66b line rates in 24.33024Gbps capable cores.

* Feature Enhancement: Added GTYE4 support for Zynq UltraScale+ devices.

* Feature Enhancement: Added support for enabling and disabling individual line rates.

* Other: Removed channel attenuation parameter. The attenuation is now set via the equalization and insertion loss parameters.

* Other: Modified management clock rate range in UltraScale devices to take user clock speeds into account.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 10)

* General: Supported devices and production status are now determined automatically, to simplify support for future devices

* Revision change in one or more subcores

Clocking Wizard (5.3)

* Version 5.3 (Rev. 2)

* Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for UltraScale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.

* Feature Enhancement: Added Matched Routing Option for better timing solutions.

* Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Other: Added support for Spartan-7 devices.

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 11)

* General: No HDL changes

* Revision change in one or more subcores

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 10)

* General: Supported devices and production status are now determined automatically, to simplify support for future devices

* Revision change in one or more subcores

Complex Multiplier (6.0)

* Version 6.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Convolution Encoder (9.0)

* Version 9.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

DDR3 SDRAM (MIG) (1.3)

* Version 1.3

* Port Change: ECC ports are added to provide status of ECC when AXI is disabled.

* Bug Fix: Added ports for proper ECC functionality and also adds the app_wdf_mask signal back to the User Interface to support Partial Writes AR67455.

* Bug Fix: Corrected issue within User Interface logic that potentially caused data errors and incorrect app_rdy behavior. AR67544

* Bug Fix: Resolved custom part issues related to moving IP, opt_design errors when skipping "Generate Output Products", and Core Container flow.  ARs 67684, 67335, and 66360.

* Feature Enhancement: Self Refresh and Save Restore support for DDR3 UI and AXI interfaces

* Feature Enhancement: MicroBlaze MCS 3.0 support.

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.1)

* Version 2.1

* Port Change: ECC ports are added to provide status of ECC when AXI is disabled.

* Bug Fix: Added ports for proper ECC functionality and also adds the app_wdf_mask signal back to the User Interface to support Partial Writes AR67455.

* Bug Fix: Enables generating 80-bit wide DDR4 interfaces for xcku115-flvf1924 FPGAs AR67632.

* Bug Fix: Corrected the speed grade of 093F to 093E AR67631.

* Bug Fix: Corrected issue within User Interface logic that potentially caused data errors and incorrect app_rdy behavior. AR67544

* Bug Fix: Resolved custom part issues related to moving IP, opt_design errors when skipping "Generate Output Products", and Core Container flow.  ARs 67684, 67335, and 66360.

* Bug Fix: Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation. DDR4 tool now properly adheres to this spec. AR66938

* Feature Enhancement: MicroBlaze MCS 3.0 support.

* Feature Enhancement: Clamshell support for DDR4 controller and Phy only mode

* Feature Enhancement: Migration support for DDR4 controller and Phy only mode

* Feature Enhancement: Parity support for DDR4 RDIMMs

* Feature Enhancement: Self Refresh and Save Restore support for AXI Interface

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 13)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

DMA Subsystem for PCI Express (PCIe) (3.0)

* Version 3.0

* Port Change: Added debug ports. When option 'Enable Debug Ports' is selected on 'PCIe DMA' tab all m_axis_rq/cc_* and s_axis_rc/cq_* signals will appear at boundary

* Bug Fix: Fixed issues with the example design generation for xcvu9p-flgc2104 and flga2577 packages

* Feature Enhancement: Added support for PCIe Gen2 devices

* Feature Enhancement: Added shared logic support for 7 series and UltraScale variants. Currently Shared logic is not supported when Tandem feature is selected.

* Feature Enhancement: Added Check parity to check parity on PCIe reads and add parity for PCIe writes. Added Parity propagate to send and receive parity bits to/from user

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 13)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Debug Bridge (1.1)

* Version 1.1

* Updated to add new modes to support XVC solution

* Revision change in one or more subcores

Decapsulator (1.0)

* Version 1.0 (Rev. 2)

* Feature Enhancement: Logic update to support RFC4175/RFC3190 packet type processing

* Feature Enhancement: Register map update

* Other: Added support for Spartan-7 devices

* Other: Removed auto OOC constraints

* Revision change in one or more subcores

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

DisplayPort (7.0)

* Version 7.0 (Rev. 2)

* Bug Fix: Fixed IEEE OUI Mapping in Rx DPCD

* Bug Fix: Issue warning when attempting to generate outside of Vivado IP Integrator

* Bug Fix: Updated OOC XDC provide constraints for all clocks and resolve Critical Warnings on clocks

* Feature Enhancement: Added option for independent synchronous/asynchronous mode to audio and programmable mask for lower bits in Maud (asynchronous mode)

* Feature Enhancement: Added audio-only mode so that in audio/video mode, info frame is sent only once per frame instead of every 512th BS symbol as well

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: HDCP IRQ Warning Fixed when validating IP Integrator BD -

* Bug Fix: Video Bridge Constraints Update - FIFO related -

* Other: Added support for GTHE4 devices, XC7K70T, XC7A25T, XC7A12T

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: HDCP IRQ Warning Fixed when validating IP Integrator BD -

* Other: Added support for GTHE4 devices, XC7K70T, XC7A25T, XC7A12T

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 11)

* Enable support for future devices

Divider Generator (5.1)

* Version 5.1 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* There have been no functional or interface changes to this IP.

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 12)

* General: Default rx_clk value changed in internal state machine logic. No functional changes.

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

FIFO Generator (13.1)

* Version 13.1 (Rev. 2)

* Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled

* Bug Fix: HASH(0x11c35f70)

* Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options

* Other: Added support for future devices

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

FIR Compiler (7.2)

* Version 7.2 (Rev. 7)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Fibre Channel 32GFC RS-FEC (1.0)

* Version 1.0

* General: Initial release

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

FlexO 100G RS-FEC (1.0)

* Version 1.0

* General: Initial release.

Floating-point (7.1)

* Version 7.1 (Rev. 3)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Framer (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fix to support non-SMPTE 2022 RTP packet processing

* Other: Added support for Spartan-7 devices

* Other: Removed auto OOC constraints

G.709 FEC Encoder/Decoder (2.2)

* Version 2.2 (Rev. 5)

* General: Comment changes in source files. No change to functionality or performance.

* Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 13)

* General: Comment changes in source files. No change to functionality or performance.

* Revision change in one or more subcores

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 13)

* General: Comment changes in source files. No change to functionality or performance.

* Revision change in one or more subcores

Gamma Correction (7.0)

* Version 7.0 (Rev. 11)

* General: Supported devices and production status are now determined automatically, to simplify support for future devices

* Revision change in one or more subcores

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 3)

* No changes

HDCP (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Cipher (1.0)

* Version 1.0

* No changes

HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0

* No changes

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Update to apply synthesis attribute to allow combinatorial loops

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fixed problem with IP Integrator FREQ_HZ parameter propagation

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fixed problem with IP Integrator FREQ_HZ parameter propagation

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

HDMI 1.4/2.0 Receiver (1.1)

* Version 1.1

* No changes

HDMI 1.4/2.0 Receiver Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: Updated DDC peripheral; solved issue with HDCP 2.2 Rx Status reads and added HDCP 1.4 KSV FIFO

* Bug Fix: Fixed issue with HDMI RX for video streams with no VIC code (VIC = 0)

* Bug Fix: Corrected issue with deep color video

* Bug Fix: Resolved Combinatorial Logic Critical Warning when enabling HDCP 2.2

* Bug Fix: Fixed HDCP mapping to suppress SUGGESTED_PRIOITY warning when validating Vivado IP Integrator design

* Bug Fix: Fixed error when setting the s_axi_cpu_aclk to something other than 100MHz

* Bug Fix: Fixed NI-DRU 10bit 12bit issue by increasing the FIFO size to 32

* Feature Enhancement: Add HDCP mode bit and HDCP 1.4 short read to DDC peripheral

* Feature Enhancement: Added new flag to the pixel packing phase output

* Feature Enhancement: Added pixel packing phase new signal

* Feature Enhancement: Added HPD and Cable Detect polarity control in GUI

* Feature Enhancement: Added HDCP auto-switching between 1.4 and 2.2

* Feature Enhancement: Added HDCP repeater mode support

* Feature Enhancement: Integrated reference design Vivado release. It is now available as Example Design. It currently supports KC705 and KCU105 Boards.

HDMI 1.4/2.0 Transmitter (1.1)

* Version 1.1

* No changes

HDMI 1.4/2.0 Transmitter Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: Resolved Combinatorial Logic Critical Warning when enabling HDCP 2.2

* Bug Fix: Fixed HDCP mapping to suppress SUGGESTED_PRIOITY warning when validating Vivado IP Integrator design

* Bug Fix: Fixed error when setting the s_axi_cpu_aclk to something other than 100MHz

* Bug Fix: Fixed DDC state machine which forced SDA data low in the last state and can cause HDCP authentication to fail

* Feature Enhancement: Added a HPD toggle function to the HDMI TX core. This update was required to solve an issue related to HDCP compliance testing.

* Feature Enhancement: Added HDCP auto-switching between 1.4 and 2.2

* Feature Enhancement: Added HDCP repeater mode support

* Feature Enhancement: Added HPD polarity control in GUI.

* Feature Enhancement: Integrated reference design Vivado release. It is now available as a Vivado Example Design. Supports KC705 and KCU105 Boards.

High Speed SelectIO Wizard (3.1)

* Version 3.1

* Bug Fix: Updated Strobe propagation logic in Advanced Strobe mode

* New Feature: Added new options in GUI, PLL phaseshift mode and Enable N-bitslice pins for RX Differential pins Refer to PG-188 for more details

* Feature Enhancement: Updated the GUI layout for Ease-Of-Use

* Feature Enhancement: Replaced PLL in core/example design radio button with checkbox

* Feature Enhancement: Removed timeouts in Reset State-machine, Refer PG-188 for more details

* Feature Enhancement: XDC Constraints updated to include PLL LOC when PLL input clock is from fabric

* Feature Enhancement: GUI option added to Select-All or Deselect-All pins in a ByteGroup

* Feature Enhancement: Removed additional blank lines at the start of generated files

* Feature Enhancement: Fine tuned Differential Pre-emphasis and Differential Termination as per IO-Standard selection

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Other: Removed Example Design support for Asynchronous Mode configuration of IP

* Other: Removed UPDATE_MODE parameter from <component name>_high_speed_selectio_wiz_v3_1.v module

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 14)

* Shortened include file names

* Added water mark.

* Revision change in one or more subcores

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 13)

* Added support for Whistler and Zynq7000 devices.

* Revision change in one or more subcores

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 14)

* Added support for xc7k70tfbv485 device

* Revision change in one or more subcores

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 11)

* Updated filenames to shorten the file lengths

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 4)

* Updated core to use latest sub-cores.

* Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 4)

* Updated core to use latest sub-cores.

* Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Correct behavior of reset (transcode bypass mode only).

* Feature Enhancement: Pad partial data output cycles with 0s (transcode bypass mode only).

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user.

* Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user.

* Revision change in one or more subcores

IEEE 802.3bj RS-FEC (1.0)

* Version 1.0 (Rev. 6)

* Feature Enhancement: Speed and area improvements to core and example design.

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user.

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2

* Updated DRC to set individual probe MU count value based on all_probe_same_mu_cnt parameter

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

IOModule (3.0)

* Version 3.0 (Rev. 6)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* General: Added wrappers for UNISIM FPGA primitives

Image Enhancement (8.0)

* Version 8.0 (Rev. 11)

* General: Supported devices and production status are now determined automatically, to simplify support for future devices

* Revision change in one or more subcores

In System IBERT (1.0)

* Version 1.0

* First release

Interlaken up to 150G (2.0)

* Version 2.0

* Port Change: Ports added for GT out of IP

* Feature Enhancement: GT outside the IP

* Feature Enhancement: IP Integrator and designer assistance support

* Feature Enhancement: Added 25 Line rate support for Ultra Scale Plus -2lV speed grade devices

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

JESD204 (7.1)

* Version 7.1

* Port Change: Added differential global clock input and removed single ended tx/rx_core_clk input. UltraScale configurations only with Shared Logic in Core. See (PG066) for information on how to drive new clock input

* Bug Fix: Fixed issue which was causing the lane ID to be incorrect in the ILA sequence: AR67349

* Other: Added support for GTYE4 devices

* Other: Added a second reset bit to the core reset register. This new bit is non self clearing and therefore allows the core to be held in reset using the reset register. The functionality of the original reset bit is unchanged

* Other: Reset logic in JESD204 Block level has been moved into separate module. No functional changes

* Other: Enabled control of Transceiver PRBS patterns via register 0x18 by increasing the register width to 5 bits. The functionality of bits 2:0 remain unchanged. See (PG066) for more information

* Revision change in one or more subcores

JESD204 PHY (3.2)

* Version 3.2

* Bug Fix: Fixed issue where CPLL PD was not being held high for at least 2us during reset. UltraScale configurations only: (Xilinx Answer 67354)

* Bug Fix: Fixed width of gt_txdiffctrl register (from 4 bits to 5) from AXI4-Lite Interface. GTYE3 configurations only

* Bug Fix: Changed default value of gt_txdiffctrl from 1000 to 1100 based on Transceiver Wizard default value. UltraScale configurations only

* Feature Enhancement: Added option to GUI to select a static or dynamic line rate configuration. See PG198 for more information

* Feature Enhancement: Added option to GUI to change Insertion loss at Nyquist value. UltraScale configurations only

* Feature Enhancement: Added new read-only registers that display start-up configuration. See PG198 for more information

* Other: Added support for GTYE4 devices

* Other: Removed BUFG_GT from txouclk and rxoutclk. UltraScale configurations only

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

JTAG to AXI Master (1.2)

* Version 1.2

* Updated logic to resume queued transaction when AXI read/write response of previous transaction is not OKAY

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 10)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* General: Added support for Spartan 7 devices

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

LTE RACH Detector (2.0)

* Version 2.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 11)

* General: Added support for Spartan-7.  No change to functionality.

* Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (2.1)

* Version 2.1

* Port Change: Added new ports based on 7-Series support (See Product Guide PG232 "Port Descriptions" section for list of added ports.)

* Bug Fix: Fixed issue with ECC corruption resulting in an invalid data type

* Bug Fix: Fixed register access issue for MIPI CSI-2 Rx Controller

* Other: Added support for 7 Series

* Other: MIPI DPHY Controller v3.0 integration

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0

* Initial release

MIPI CSI-2 Tx Subsystem (1.0)

* Version 1.0

* General: Initial release

* General: Support for 7 Series, Zynq 7000, UltraScale+, Zynq UltraScale+ MPSoC

* General: Subsystem with integrated MIPI DPHY Controller and CSI-2 Tx Controller.

* General: Support for 1 to 4 DPHY lanes

* General: AXI4-Stream and Native Video Input interface selection

MIPI D-PHY (3.0)

* Version 3.0

* Port Change: Added new ports based on 7 Series support (See Product Guide PG202 "Port Descriptions" section for list of added ports.)

* Port Change: Added active_lanes_in[3:0] port for Active lane support (See Product Guide PG202 "Port Descriptions" section for list of added ports.)

* Bug Fix: Fixed SoT pattern logic detection in D-PHY RX IP

* New Feature: Added 7-Series family support

* New Feature: Added active lanes support in D-PHY TX

* Other: High-Speed SelectIO v3.1 IP integration

* Other: Revision change in one or more subcores

* Revision change in one or more subcores

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

MIPI DSI Tx Subsystem (1.1)

* Version 1.1

* Port Change: Added new ports based on 7 Series support (See Product Guide PG238 "Port Descriptions" section for list of added ports.)

* Other: Added support for 7 Series

* Other: MIPI DPHY Controller v3.0 integration

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 7)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

Memory Helper Core (1.3)

* Version 1.3

* Support for Vivado 2016.3

Memory Interface Generator (MIG 7 Series) (4.0)

* Version 4.0 (Rev. 1)

* New Feature: Added GUI option in Memory Controller Options page for number of Bank Machines selection.

* Other: Beta Support for Spartan-7 devices.

MicroBlaze (10.0)

* Version 10.0

* Port Change: Added parallel debug access signals

* Bug Fix: Do not fetch instructions for sleep reset mode. Versions that have this issue: 9.4, 9.5, 9.6. Can only occur when debug is disabled and using Reset_Mode.

* Bug Fix: Ensure that interrupts do not interfere with debug stepping. Versions that have this issue: 9.3, 9.4, 9.5, 9.6.

* Feature Enhancement: Updated with frequency optimized 8-stage pipeline

* Feature Enhancement: Provide parallel synchronous debug access

* Feature Enhancement: Included additional MSR reset value parameter choices

* Feature Enhancement: Added additional AXI bus interface properties

* Feature Enhancement: Automatically adjust boot loop ELF to match Vector Base Address

* Other: Added support for Spartan-7 devices

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 7)

* Port Change: Added parallel debug access signals

* Feature Enhancement: Provide parallel synchronous debug access

* Feature Enhancement: Added additional AXI bus interface properties

* Feature Enhancement: Defined bus interface for external BSCAN signals

* Feature Enhancement: Option to disable BSCAN when using debug register access from AXI

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Other: Added wrappers for UNISIM FPGA primitives

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 2)

* General: Updated with latest subcores

* General: Added support for Spartan-7 devices

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Multiply Adder (3.0)

* Version 3.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Mutex (2.1)

* Version 2.1 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Added ASPM option to enable the data filtering in L0s state

* Bug Fix: Correction in GT reset sequence during the rate change

* Bug Fix: Change in CDRHold logic to ensure the CDR and RX equalization logic functions correctly and avoids invalid data

* Feature Enhancement: Added xcku115 device support

* Feature Enhancement: Added Gen4 Support for UltraScale+ devices xcvu3p-ffvc1517 and xczu9eg-ffvb1156

* Feature Enhancement: Added Spec 0.7 EIEOS Support for Gen4

* Revision change in one or more subcores

Partial Reconfiguration Controller (1.1)

* Version 1.1

* Bug Fix: Fixed some issues with FETCH error handling if the error occurred on the first word of a transfer.

* Bug Fix: Fixed a bug where the core failed to generate if the chosen part was an UltraScale+ part.

* Bug Fix: Fixed a bug in the CAP arbitration code. Bitstream transfers would not start if CAP_REL was hardwired to 1.

* New Feature: Added support for UltraScale+

* Feature Enhancement: Updated the CAP arbitration protocol to support three modes. See the Product Guide for more information.

* Feature Enhancement: Small change made to the customization GUI.

* Other: Updated the fifo_generator to v13.1.

* Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 3)

* Changed the default library for the demonstration testbench to xil_defaultlib.

Peak Cancellation Crest Factor Reduction (6.1)

* Version 6.1

* Feature Enhancement: Support to work as Stand-alone Hard Clipper.

* Feature Enhancement: Support for WCFR as a post processing stage when CFR stage has PC-CFR with smart peak processing disabled.

* Feature Enhancement: Support for WCFR to operate with and without Smart Peak Processing.

* Feature Enhancement: TUSER forwarding. TUSER will be delay matched with actual datapath.

* Feature Enhancement: Support for additional two more RATs RATD, RATE in dynamic CP computation mode

* Revision change in one or more subcores

Processor System Reset (5.0)

* Version 5.0 (Rev. 10)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

QDRII+ SRAM (MIG) (1.3)

* Version 1.3

* Port Change:

* Feature Enhancement: MicroBlaze MCS 3.0 support.

* Revision change in one or more subcores

QDRIV SRAM (MIG) (1.2)

* Version 1.2

* Port Change:

* Feature Enhancement: MicroBlaze MCS 3.0 support.

* Revision change in one or more subcores

QDRIV SRAM PHY IP (1.2)

* Version 1.2

* Support for Vivado 2016.3

QSGMII (3.3)

* Version 3.3 (Rev. 6)

* General: Changed version of helper core gig_ethernet_pcs_pma from v15_2 to v16_0

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 10)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

RFC3190 De-Packetizer (1.0)

* Version 1.0

* General: Initial Release

* General: 1-16 audio channels

* General: Audio sample encoding schemes (also called word length) - 12, 16, 20, 24

RFC3190 Packetizer (1.0)

* Version 1.0

* General: Initial Release

* General: 1-16 audio channels

* General: Audio sample encoding schemes (also called word length) - 12, 16, 20, 24

RFC4175 De-packetizer (1.0)

* Version 1.0

* General: Initial Release

* General: Pixel per clock support: 1, 2, 4

* General: Bits per sample support: 8, 10, 12, 16

* General: Video format support: RGB, YCbCr 4:4:4,YCbCr 4:2:2 (Progressive/Interlaced)

RFC4175 Packetizer (1.0)

* Version 1.0

* General: Initial Release

* General: Pixel per clock support: 1, 2, 4

* General: Bits per sample support: 8, 10, 12, 16

* General: Video format support: RGB, YCbCr 4:4:4,YCbCr 4:2:2 (Progressive/Interlaced)

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 9)

* General: Added auto family support

* Revision change in one or more subcores

RLDRAM3 (MIG) (1.3)

* Version 1.3

* Port Change: Updated the address width for 1.125Gb X36 Part as 20 instead of 21 AR67367.

* Bug Fix: Updated the address width for 1.125Gb X36 Part as 20

* Feature Enhancement: MicroBlaze MCS 3.0 support.

* Revision change in one or more subcores

RXAUI (4.3)

* Version 4.3 (Rev. 6)

* Bug Fix: Changed "IBUF_LOW_PWR" parameter from TRUE to FALSE for IBUFs instantiated at the input of refclk_p/n

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 12)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 11)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

S/PDIF (2.0)

* Version 2.0 (Rev. 13)

* General: No functional changes

* Revision change in one or more subcores

SC EXIT (1.0)

* Version 1.0 (Rev. 2)

* Bug fixes

SC MMU (1.0)

* Version 1.0 (Rev. 2)

* Added SUPPORTS_{READ|WRITE}_DECERR parameter to enable/disable the decode error rejection logic.

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fix write burst-length corruption for transactions that split into 3 or more parts due to downsizing or AXI3 conversion.

* New Feature: Added HDL code to support packet-mode regulation of AW and AR commands.

* New Feature: Added HDL code and parameter ranges to support multi-threading (for all transactions).

SC SPLITTER (1.0)

* Version 1.0 (Rev. 1)

* No changes

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 2)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

SMPTE 2022-1/2 Video over IP Receiver (2.0)

* Version 2.0 (Rev. 7)

* General: Added Spartan-7 device support

* General: moved all the clocks to auto constraint generation, so as to allow OOC XDC constraints to be generated implicitly

* Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

* Version 2.0 (Rev. 7)

* Bug Fix: Fixed AXI MM interface hanging if WREADY is not asserted immediately for AR65268

* Other: Added Spartan-7 device support

* Other: moved all the clocks to auto constraint generation, so as to allow OOC XDC constraints to be generated implicitly

* Revision change in one or more subcores

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* Bug Fix: fixed the incorrect operation of rx_sd_data_strobe getting asserted for more than 50 percent

SMPTE ST 2059 (1.0)

* Version 1.0 (Rev. 1)

* General: Added Spartan-7 device support

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 3)

* Bug Fix: 1080p48 transport mode will be detected and t_locked signal will assert high.

* Bug Fix: Removed support Zynq 7000 -1 speed grade parts with Artix-7 Fabric (AR 59601)

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user.)

SMPTE2022-5/6 Video over IP Receiver (5.0)

* Version 5.0 (Rev. 6)

* Bug Fix: Fixed clearing of core internal buffer status upon channel disable did not update certain flag properly, resulting in disallowing packet write after channel

* Bug Fix: Fixed initial latching of the sequence number for buffer calculation is not on the right signal resulting in wrong buffer level

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user)

* Other: Moved all the clocks to auto constraint generation, so as to allow OOC XDC constraints to be generated implicitly

* Revision change in one or more subcores

SMPTE2022-5/6 Video over IP Transmitter (4.0)

* Version 4.0 (Rev. 8)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user)

* General: Moved all the clocks to auto constraint generation, so as to allow OOC XDC constraints to be generated implicitly

* Revision change in one or more subcores

SPI-4.2 (13.0)

* Version 13.0 (Rev. 9)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

ST2022-56 De-Packetizer (1.0)

* Version 1.0 (Rev. 2)

* General: Added support for Spartan-7 devices

ST2022-56 Packetizer (1.0)

* Version 1.0 (Rev. 2)

* General: Added support for Spartan-7 devices

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 8)

* Feature Enhancement: Added option in GUI to set the high performance mode for IODELAY

* Other: Spartan-7 device support added

Serial RapidIO Gen2 (4.0)

* Version 4.0 (Rev. 5)

* Feature Enhancement: Added support for GTY transceiver in UltraScale and UltraScale Plus devices

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 2)

* Reduce synthesis runtime by having dynamic PAYLD

SmartConnect Node (1.0)

* Version 1.0 (Rev. 2)

* Implement FIFOs with xpm_fifo.

* Revision change in one or more subcores

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 2)

* Reduce synthesis runtime by having dynamic PAYLD

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 2)

* Reduce synthesis runtime by having dynamic PAYLD

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 7)

* General: Add Beta support for new devices XC7A25T,XC7A12T,XC7S25,XC7S50,XC7Z007S,XC7Z012S,XC7Z014S

System Cache (4.0)

* Version 4.0

* Port Change: Added ACE signals to Master ports

* Feature Enhancement: Added Master ACE support for UltraScale+ MPSoC PS Coherency

* Feature Enhancement: Added 64-bit support on Control interface

* Feature Enhancement: Added optional Secure transaction support

* Feature Enhancement: Added optional processing of AXI errors

* Feature Enhancement: Added support for Allocation and Buffer override

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Other: Added support for Spartan-7 devices

System ILA (1.0)

* Version 1.0

* Native Vivado Release

* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

System Management Wizard (1.3)

* Version 1.3 (Rev. 2)

* General: Internal GUI changes, no effect on the customer designs.

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* Updated XDC to add RLOC constraints for CDC flops in timer_bit_sample module

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 6)

* Bug Fix: Updated TX path latency values for 1588

* Other: Spartan-7 Pre-Production support

* Other: Updated example design XDC to bypass PDRC-203 for UltraScale and UltraScale+ devices having reference PIN LOCs

* Other: Improved GUI speed and responsiveness, no functional changes

* Revision change in one or more subcores

UltraScale 100G Ethernet Subsystem (2.0)

* Version 2.0

* Port Change: gtwiz_reset_tx_datapath and gtwiz_reset_rx_datapath ports are available by default

* Port Change: Added gt_txinhibit input port to the GT if Enable Additional GT Control/Status and DRP Ports is selected

* Port Change: Added IO ports for GT out of core feature support

* Feature Enhancement: GT out of core feature support

* Feature Enhancement: Added IP Integrator Designer Assistance support

* Other: Standard DRP interface vlnv used for DRP ports for IP Integrator design

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.2)

* Version 4.2 (Rev. 2)

* Port Change: Added optional debug signals for IBERT and JTAG debug in the Additional Transceiver Control and Status Ports.

* Bug Fix: Fix is added in the gtwizard_top module for a link up issue.

* Bug Fix: Added de-skew logic for Gen3x4 and Gen3x2 in 250 MHz CORE CLOCK Frequency.

* Bug Fix: Updated the Tandem constraints to additionally filter primitive by primitive_level.

* Feature Enhancement: Added JTAG debugger support in the Add. Debug Options GUI page to debug LTSSM, Reset sequence and Rx detect sequence.

* Feature Enhancement: Added In-System IBERT support in the Add. Debug Options GUI page.

* Feature Enhancement: Added Descrambler debug support in the Add. Debug Options GUI page to debug PIPE data.

* Feature Enhancement: Added Auto Rx Equalization support in the GT Settings GUI page.

* Other: The location and format of generated output files has been updated.

* Other: Updated the default MCAP Bitstream ID register value for 2016.3.

* Other: Added parameter Enable Parity on Basic page in Advanced mode.

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.6)

* Version 1.6 (Rev. 4)

* Feature Enhancement: Added new transceiver configuration preset options for GTY-JESD/CEI

* Feature Enhancement: Added new Structural Options to include In-System IBERT core in Example Design

* Other: SIM_VERSION to SIM_DEVICE migration for GTYE4/GTHE4 UNISIM primitives

* Other: Enhanced QPLL Fractional-N calculator feature in the Wizard customization GUI to extend support to 28.21 Gb/s

* Other: Updated transceiver configuration preset options for Gigabit Ethernet KR configuration

* Other: Improved load time of the Wizard customization GUI, and its responsiveness

* Other: Updated the line rate ranges for -2LV/-1LV speed grade devices to match the UltraScale+ FPGAs Data sheet

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 2)

* General: Add support for all monolithic UltraScale+ devices

* General: Enable Error Classification and Diagnostic Scan features for all monolithic UltraScale+ devices

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

UltraScale+ 100G Ethernet Subsystem (2.0)

* Version 2.0

* Port Change: gtwiz_reset_tx_datapath and gtwiz_reset_rx_datapath ports are available by default

* Port Change: Added gt_txinhibit input port to the GT if Enable Additional GT Control/Status and DRP Ports is selected

* Port Change: Added IO ports for GT out of core feature support

* Feature Enhancement: GT out of core feature support

* Feature Enhancement: Enabled RX GT buffer bypass Single-lane mode

* Other: Added support for xcvu11p-fsgd2104, xcvu13p-figd2104, xcvu9p-fsgd2104 devices

* Other: Standard DRP interface vlnv used for DRP ports for IP Integrator design

* Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.1)

* Version 1.1 (Rev. 2)

* Port Change: No mandatory port changes. But added new optional ports and interfaces for PCIe DRP, GT DRP, GT Wizard, In System IBERT, Transceiver Control and Status ports.

* Bug Fix: Enabled ASPM L0s.

* Bug Fix: Added PMARESET fix, update to the GT reset sequence during the rate change.

* Bug Fix: Added CDRHOLD fix to ensure CDR and RX Equalization to start working first and not give any false indication that data is good already.

* Bug Fix: Added Sequence number FIFO fix for ES2 silicon.

* Feature Enhancement: Added GT DRP, PCIe DRP and Transceiver Control and Status ports option in the core configuration GUI.

* Feature Enhancement: Added simulation model support to run post synthesis and post implementation simulation.

* Feature Enhancement: Added support for 125 MHz and 250 MHz reference clock option.

* Feature Enhancement: Added GT Wizard support for Xilinx example design in the Shared Logic page.

* Feature Enhancement: Added In-System IBERT support in the Add. Debug Options page to scan eye diagram of the serial lane

* Feature Enhancement: Added JTAG debugger support in the Add. Debug Options page to debug LTSSM, Rx sequence, Rx detect.

* Feature Enhancement: Added Descrambler debug support in the Add. Debug Options page to debug PIPE data.

* Other: Moved pblock constraints from IP level XDC file to Xilinx example design top XDC file to allow users to access SLICE range settings in 512-bit AXIST mode.

* Revision change in one or more subcores

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 13)

* gui_tcl is changed to 2.0

* Revision change in one or more subcores

Video AXI4S Remapper (1.0)

* Version 1.0 (Rev. 2)

* General: Updated example design for 2016.3

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 4)

* General: Updated example design for 2016.3

* Revision change in one or more subcores

Video Deinterlacer (4.0)

* Version 4.0 (Rev. 11)

* Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user.)

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 4)

* Feature Enhancement: Added 8 pixels per clock support

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation (No changes required by the user.)

* Other: Updated to use FIFO Generator v13.1

* Revision change in one or more subcores

Video Mixer (1.0)

* Version 1.0 (Rev. 2)

* Feature Enhancement: Added per-pixel support of alpha-blending of eight video/graphics and logo layers

* Feature Enhancement: Added support for YUV 4:2:0

* Feature Enhancement: Added 10-bit per color component support on memory interface

* Other: Supported devices and production status are determined automatically, to simplify support for future devices

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 12)

* General: Added auto family support

* Revision change in one or more subcores

Video PHY Controller (2.0)

* Version 2.0 (Rev. 3)

* General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* General: Fixed file name confliction when 2 IP instances in the same block design

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Feature Enhancement: Added format conversion to Scaler Only functionality (convert between RGB, YUV 4:4:4, YUV 4:2:2, and YUV 4:2:0)

* Feature Enhancement: Added pass through feature to Chroma Resampling functionality (no resampling performed if input and output video formats are the same)

* Feature Enhancement: Added YUV 4:2:0 support to Deinterlacing Only functionality

* Other: Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces aclk, aclk_axis, aclk_axi_mm, and aclk_ctrl

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 4)

* Feature Enhancement: Increased maximum resolution to 8192x4320

* Feature Enhancement: Supported 8 samples per clock

* Feature Enhancement: Supported DisplayPort test patterns

* Feature Enhancement: More configurability, i.e. allow which test patterns to compile in/out

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 9)

* Bug Fix: Fixed GUI to prevent disablement of all generation and detection signals.

* Bug Fix: Fixed GUI for synchronize generator to detector or fsync_in behavior.

Video over IP FEC Receiver (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: Increased register response timeout to improve reading buffer status when servicing multiple high bandwidth bit streams

* Feature Enhancement: Logic update to support RFC4175/RFC3190 packet type processing

* Other: Added support for Spartan-7 devices

* Revision change in one or more subcores

Video over IP FEC Transmitter (2.0)

* Version 2.0 (Rev. 2)

* Feature Enhancement: Logic update to support RFC4175/RFC3190 packet type processing

* Other: Added support for Spartan-7 devices

* Revision change in one or more subcores

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)

* Version 4.2 (Rev. 2)

* Feature Enhancement: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Other: Added support for FLG1155/FLG1931 packages for xc7vh580t device, FLG1931 for xc7vh870t device, FFV1156/FFV1761 for xc7vx330t device, FFV1157/FFV1158/FFV1927 for xc7vx415T device

* Revision change in one or more subcores

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 7)

* General: Support for Spartan-7 devices

* Revision change in one or more subcores

XADC Wizard (3.3)

* Version 3.3 (Rev. 1)

* Bug Fix: Updated the voltage alarm ranges.

* Other: Added support for Spartan-7 devices.

XAUI (12.2)

* Version 12.2 (Rev. 6)

* Port Change: Added refclk_out port, which is required for GT reference clock sharing across adjacent quads

* Bug Fix: Changed "IBUF_LOW_PWR" parameter from TRUE to FALSE for IBUFs instantiated at the input of refclk_p/n

* Bug Fix: Fixed to use BUFH as a default buffer for forwarding GT refclk in CPLL railing module

* Feature Enhancement: Added option to switch mapping of lanes between core and GT

* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0

* General: Initial release

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 9)

* General: Added auto family support

* Revision change in one or more subcores

ZYNQ UltraScale+ MPSoC (2.0)

* Version 2.0

* 1) Multiple changes in parameters for Zynq UltraScale+ MPSoC. As a result of this, upgrade from project prior to 2016.3 may break, requiring reentry of settings. Please refer to (Xilinx Answer 67861) for upgrade details.

* Reasons for parameters changes

  1. Removed unused parameters
  2. Enhanced DRCs for certain parameters
  3. Values of certain parameters changed from previous releases

*

* 2) Enabled Isolation configuration in Processor Configuration Wizard  to support memory protection through XMPU and LPD peripherals protection through XPPU.

* Note: Isolation configuration is supported for all devices except ZU9-ES1

*

* 3) I/O Configuration

  1. SD & eMMC interfaces enhanced to support SD 2.0 (4-bit data transfer mode) SD 3.0 (8-bit data transfer mode). eMMC supports both 4-bit and 8-bit data transfer modes.
  2. WDT and TTC enabled to be driven by either internal clock, or using clock through MIO or EMIO.
  3. In Processor Configuration Wizard, QSPI in "Dual Parallel" mode only support x4 data mode. x1 & x2 data modes are not supported by BOOR ROM for QSPI in "Dual Parallel" mode hence removed. For Single and Dual Stacked modes (not parallel) x1 and x2 are supported.
  4. For SPI interface, updated MIO pin choices to make sure all pins are from the same MIO bank. Slave Select port has been changed from a vector to 3 scalar ports.
  5. Fixed non allowed MIO / EMIO pins selection for certain LPD peripherals -
  6. Other bug fixes

*

* 4) Clock Configuration

 

  1. Multiple enhancements in clock configuration through Processor Configuration Wizard
  2. Change in GUI layout, introduced tabs as "Input Clocks" for input PLL selection and "Output Clocks" for peripheral clocks.
  3. Manual mode and Automatic mode are in a single tab under "Output Clocks" with both modes being mutually exclusive.
  4. Enabled multiple DRCs on clock configurations.
  5. Specific DRC added for timestamp, LPD and FPD clocks as follows -

 

  • Dbg_tstmp_clk must never run faster than dbg_lpd_clk or dbg_fpd_clk
  • Dbg_tstmp_clk must never be disabled when dbg_lpd_clk or dbg_fpd_clk are running


  6. Other bug fixes

*

* 5) DDR Configuration

  1. Enhanced ease of use by keeping controller configuration under "DDR Controller Options" tree, memory part related configuration under "DDR Memory Options" tree and other low level configuration under "Other Options" tree
  2. Enabled DRCs based on memory part
  3. A TcL parameter is added for vendor specific memory part configuration. The parameter name is PSU__DDRC__VENDOR_PART
  4. A TcL parameter is added to disable clock buffers in Zynq UltraScale+ MPSoC wrapper. The parameter is PSU__PL_CLK0_BUF
  5. For dual die, dual rank packages, maximum size for LPDDR4 components updated to 16Gb.
  6. Added support for UDIMM & RDIMM components
  7. Other bug fixes

*

* 6) PS-PL Configuration

* Added support for PL to PS legacy interrupts

*

* 7) PCIe Configuration

  1. For PCIe as EP MSI vectors limited to 4
  2. PCIe lane selection is decided based on PCIe lane configuration with the choices as x1, x2, x4
  3. MSI-X attributes updated for Table and PBA offsets.
  4. ECRC generation disabled for ES1 devices
  5. Other bug fixes

*

* 8) GT/Serdes Configuration

  1. Enhancements and corrections for GT lane reference clock configuration
  2. Eyescan enable turned on by default for all GT based protocols
  3. Enhancements to improve the SerDes performance, reliability, extreme temperature and across different process corners through optimal ILL register settings.
  4. Added vendor specific PHY configuration values for SATA for optimal performance.
  5. Other bug fixes

 

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 4)

* Added support for Zynq-7000 single core devices

* Fixed XDC file generation for CLG225 devices.

* Added Tcl parameters to force AxCACHE[1] = 1 for M_GPx AXI PL interfaces. Parameter names are "PCW_GP0_EN_MODIFIABLE_TXN" and "PCW_GP1_EN_MODIFIABLE_TXN".

* Performance improvement for DDR initialization when ECC is enabled.

ZYNQ7 Processing System BFM (2.0)

* Version 2.0 (Rev. 5)

* No changes

axi_sg (4.1)

* Version 4.1 (Rev. 4)

* Revision change in one or more subcores

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 6)

* Updates for Spartan-7 device family

* Using Full and wr_rst_busy as per FIFO guidelines

* Revision change in one or more subcores

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

 

AR# 68021
Date Created 10/03/2016
Last Updated 10/13/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2016.3